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https://github.com/yuzu-emu/yuzu.git
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266 lines
9.8 KiB
C++
266 lines
9.8 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <cstddef>
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#include <string>
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#ifndef _MSC_VER
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#include <type_traits> // for std::enable_if
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#endif
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/vector_math.h"
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#include "video_core/regs_framebuffer.h"
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#include "video_core/regs_lighting.h"
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#include "video_core/regs_pipeline.h"
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#include "video_core/regs_rasterizer.h"
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#include "video_core/regs_texturing.h"
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namespace Pica {
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// Returns index corresponding to the Regs member labeled by field_name
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// TODO: Due to Visual studio bug 209229, offsetof does not return constant expressions
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// when used with array elements (e.g. PICA_REG_INDEX(vs_uniform_setup.set_value[1])).
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// For details cf.
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// https://connect.microsoft.com/VisualStudio/feedback/details/209229/offsetof-does-not-produce-a-constant-expression-for-array-members
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// Hopefully, this will be fixed sometime in the future.
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// For lack of better alternatives, we currently hardcode the offsets when constant
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// expressions are needed via PICA_REG_INDEX_WORKAROUND (on sane compilers, static_asserts
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// will then make sure the offsets indeed match the automatically calculated ones).
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#define PICA_REG_INDEX(field_name) (offsetof(Pica::Regs, field_name) / sizeof(u32))
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#if defined(_MSC_VER)
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#define PICA_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) (backup_workaround_index)
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#else
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// NOTE: Yeah, hacking in a static_assert here just to workaround the lacking MSVC compiler
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// really is this annoying. This macro just forwards its first argument to PICA_REG_INDEX
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// and then performs a (no-op) cast to size_t iff the second argument matches the expected
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// field offset. Otherwise, the compiler will fail to compile this code.
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#define PICA_REG_INDEX_WORKAROUND(field_name, backup_workaround_index) \
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((typename std::enable_if<backup_workaround_index == PICA_REG_INDEX(field_name), \
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size_t>::type)PICA_REG_INDEX(field_name))
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#endif // _MSC_VER
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struct Regs {
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INSERT_PADDING_WORDS(0x10);
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u32 trigger_irq;
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INSERT_PADDING_WORDS(0x2f);
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RasterizerRegs rasterizer;
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TexturingRegs texturing;
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FramebufferRegs framebuffer;
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LightingRegs lighting;
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PipelineRegs pipeline;
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struct ShaderConfig {
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BitField<0, 16, u32> bool_uniforms;
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union {
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BitField<0, 8, u32> x;
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BitField<8, 8, u32> y;
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BitField<16, 8, u32> z;
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BitField<24, 8, u32> w;
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} int_uniforms[4];
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INSERT_PADDING_WORDS(0x4);
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union {
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// Number of input attributes to shader unit - 1
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BitField<0, 4, u32> max_input_attribute_index;
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};
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// Offset to shader program entry point (in words)
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BitField<0, 16, u32> main_offset;
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/// Maps input attributes to registers. 4-bits per attribute, specifying a register index
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u32 input_attribute_to_register_map_low;
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u32 input_attribute_to_register_map_high;
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unsigned int GetRegisterForAttribute(unsigned int attribute_index) const {
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u64 map = ((u64)input_attribute_to_register_map_high << 32) |
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(u64)input_attribute_to_register_map_low;
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return (map >> (attribute_index * 4)) & 0b1111;
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}
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BitField<0, 16, u32> output_mask;
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// 0x28E, CODETRANSFER_END
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INSERT_PADDING_WORDS(0x2);
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struct {
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enum Format : u32 {
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FLOAT24 = 0,
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FLOAT32 = 1,
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};
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bool IsFloat32() const {
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return format == FLOAT32;
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}
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union {
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// Index of the next uniform to write to
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// TODO: ctrulib uses 8 bits for this, however that seems to yield lots of invalid
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// indices
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// TODO: Maybe the uppermost index is for the geometry shader? Investigate!
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BitField<0, 7, u32> index;
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BitField<31, 1, Format> format;
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};
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// Writing to these registers sets the current uniform.
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u32 set_value[8];
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} uniform_setup;
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INSERT_PADDING_WORDS(0x2);
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struct {
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// Offset of the next instruction to write code to.
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// Incremented with each instruction write.
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u32 offset;
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// Writing to these registers sets the "current" word in the shader program.
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u32 set_word[8];
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} program;
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INSERT_PADDING_WORDS(0x1);
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// This register group is used to load an internal table of swizzling patterns,
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// which are indexed by each shader instruction to specify vector component swizzling.
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struct {
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// Offset of the next swizzle pattern to write code to.
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// Incremented with each instruction write.
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u32 offset;
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// Writing to these registers sets the current swizzle pattern in the table.
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u32 set_word[8];
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} swizzle_patterns;
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INSERT_PADDING_WORDS(0x2);
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};
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ShaderConfig gs;
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ShaderConfig vs;
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INSERT_PADDING_WORDS(0x20);
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// Map register indices to names readable by humans
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// Used for debugging purposes, so performance is not an issue here
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static std::string GetCommandName(int index);
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static constexpr size_t NumIds() {
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return sizeof(Regs) / sizeof(u32);
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}
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const u32& operator[](int index) const {
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const u32* content = reinterpret_cast<const u32*>(this);
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return content[index];
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}
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u32& operator[](int index) {
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u32* content = reinterpret_cast<u32*>(this);
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return content[index];
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}
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private:
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/*
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* Most physical addresses which Pica registers refer to are 8-byte aligned.
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* This function should be used to get the address from a raw register value.
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*/
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static inline u32 DecodeAddressRegister(u32 register_value) {
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return register_value * 8;
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}
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};
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// TODO: MSVC does not support using offsetof() on non-static data members even though this
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// is technically allowed since C++11. This macro should be enabled once MSVC adds
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// support for that.
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#ifndef _MSC_VER
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(trigger_irq, 0x10);
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ASSERT_REG_POSITION(rasterizer, 0x40);
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ASSERT_REG_POSITION(rasterizer.cull_mode, 0x40);
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ASSERT_REG_POSITION(rasterizer.viewport_size_x, 0x41);
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ASSERT_REG_POSITION(rasterizer.viewport_size_y, 0x43);
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ASSERT_REG_POSITION(rasterizer.viewport_depth_range, 0x4d);
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ASSERT_REG_POSITION(rasterizer.viewport_depth_near_plane, 0x4e);
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ASSERT_REG_POSITION(rasterizer.vs_output_attributes[0], 0x50);
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ASSERT_REG_POSITION(rasterizer.vs_output_attributes[1], 0x51);
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ASSERT_REG_POSITION(rasterizer.scissor_test, 0x65);
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ASSERT_REG_POSITION(rasterizer.viewport_corner, 0x68);
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ASSERT_REG_POSITION(rasterizer.depthmap_enable, 0x6D);
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ASSERT_REG_POSITION(texturing, 0x80);
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ASSERT_REG_POSITION(texturing.texture0_enable, 0x80);
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ASSERT_REG_POSITION(texturing.texture0, 0x81);
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ASSERT_REG_POSITION(texturing.texture0_format, 0x8e);
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ASSERT_REG_POSITION(texturing.fragment_lighting_enable, 0x8f);
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ASSERT_REG_POSITION(texturing.texture1, 0x91);
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ASSERT_REG_POSITION(texturing.texture1_format, 0x96);
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ASSERT_REG_POSITION(texturing.texture2, 0x99);
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ASSERT_REG_POSITION(texturing.texture2_format, 0x9e);
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ASSERT_REG_POSITION(texturing.tev_stage0, 0xc0);
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ASSERT_REG_POSITION(texturing.tev_stage1, 0xc8);
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ASSERT_REG_POSITION(texturing.tev_stage2, 0xd0);
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ASSERT_REG_POSITION(texturing.tev_stage3, 0xd8);
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ASSERT_REG_POSITION(texturing.tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(texturing.fog_mode, 0xe0);
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ASSERT_REG_POSITION(texturing.fog_color, 0xe1);
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ASSERT_REG_POSITION(texturing.fog_lut_offset, 0xe6);
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ASSERT_REG_POSITION(texturing.fog_lut_data, 0xe8);
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ASSERT_REG_POSITION(texturing.tev_stage4, 0xf0);
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ASSERT_REG_POSITION(texturing.tev_stage5, 0xf8);
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ASSERT_REG_POSITION(texturing.tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(framebuffer, 0x100);
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ASSERT_REG_POSITION(framebuffer.output_merger, 0x100);
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ASSERT_REG_POSITION(framebuffer.framebuffer, 0x110);
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ASSERT_REG_POSITION(lighting, 0x140);
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ASSERT_REG_POSITION(pipeline, 0x200);
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ASSERT_REG_POSITION(pipeline.vertex_attributes, 0x200);
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ASSERT_REG_POSITION(pipeline.index_array, 0x227);
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ASSERT_REG_POSITION(pipeline.num_vertices, 0x228);
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ASSERT_REG_POSITION(pipeline.vertex_offset, 0x22a);
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ASSERT_REG_POSITION(pipeline.trigger_draw, 0x22e);
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ASSERT_REG_POSITION(pipeline.trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(pipeline.vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(pipeline.command_buffer, 0x238);
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ASSERT_REG_POSITION(pipeline.gpu_mode, 0x245);
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ASSERT_REG_POSITION(pipeline.triangle_topology, 0x25e);
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ASSERT_REG_POSITION(pipeline.restart_primitive, 0x25f);
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ASSERT_REG_POSITION(gs, 0x280);
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ASSERT_REG_POSITION(vs, 0x2b0);
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#undef ASSERT_REG_POSITION
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#endif // !defined(_MSC_VER)
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static_assert(sizeof(Regs::ShaderConfig) == 0x30 * sizeof(u32),
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"ShaderConfig structure has incorrect size");
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// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value
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// anyway.
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static_assert(sizeof(Regs) <= 0x300 * sizeof(u32),
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"Register set structure larger than it should be");
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static_assert(sizeof(Regs) >= 0x300 * sizeof(u32),
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"Register set structure smaller than it should be");
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/// Initialize Pica state
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void Init();
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/// Shutdown Pica state
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void Shutdown();
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} // namespace
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