2022-04-23 08:59:50 +00:00
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// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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2016-09-02 03:07:14 +00:00
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2021-04-14 23:07:40 +00:00
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#include "common/settings.h"
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2023-06-13 01:34:25 +00:00
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#include "core/arm/dynarmic/arm_dynarmic.h"
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2020-03-02 04:46:10 +00:00
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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2023-06-13 01:34:25 +00:00
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#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
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2018-01-09 21:33:46 +00:00
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#include "core/core_timing.h"
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2021-04-24 05:04:28 +00:00
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#include "core/hle/kernel/k_process.h"
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2018-01-09 21:33:46 +00:00
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2018-08-25 01:43:32 +00:00
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namespace Core {
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2018-02-09 00:04:05 +00:00
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using Vector = Dynarmic::A64::Vector;
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2021-06-23 21:18:27 +00:00
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using namespace Common::Literals;
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2018-02-09 00:04:05 +00:00
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2020-03-02 04:46:10 +00:00
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class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
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public:
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explicit DynarmicCallbacks64(ArmDynarmic64& parent, const Kernel::KProcess* process)
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: m_parent{parent}, m_memory(process->GetMemory()),
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m_process(process), m_debugger_enabled{parent.m_system.DebuggerEnabled()},
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m_check_memory_access{m_debugger_enabled ||
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!Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
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2018-01-09 21:33:46 +00:00
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2018-01-13 22:34:15 +00:00
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u8 MemoryRead8(u64 vaddr) override {
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2022-06-06 16:56:01 +00:00
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CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read);
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2023-11-28 19:30:39 +00:00
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return m_memory.Read8(vaddr);
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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u16 MemoryRead16(u64 vaddr) override {
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2022-06-06 16:56:01 +00:00
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CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read);
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2023-11-28 19:30:39 +00:00
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return m_memory.Read16(vaddr);
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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u32 MemoryRead32(u64 vaddr) override {
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2022-06-06 16:56:01 +00:00
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CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read);
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2023-11-28 19:30:39 +00:00
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return m_memory.Read32(vaddr);
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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u64 MemoryRead64(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
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return m_memory.Read64(vaddr);
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2018-01-09 21:33:46 +00:00
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}
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2018-02-09 00:04:05 +00:00
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Vector MemoryRead128(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Read);
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return {m_memory.Read64(vaddr), m_memory.Read64(vaddr + 8)};
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2018-02-09 00:04:05 +00:00
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}
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2022-06-21 00:39:16 +00:00
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std::optional<u32> MemoryReadCode(u64 vaddr) override {
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if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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2022-06-21 00:39:16 +00:00
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return std::nullopt;
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}
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2023-11-28 19:30:39 +00:00
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return m_memory.Read32(vaddr);
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2022-06-21 00:39:16 +00:00
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}
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2018-01-09 21:33:46 +00:00
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2018-01-13 22:34:15 +00:00
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void MemoryWrite8(u64 vaddr, u8 value) override {
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if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
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2023-11-28 19:30:39 +00:00
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m_memory.Write8(vaddr, value);
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}
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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void MemoryWrite16(u64 vaddr, u16 value) override {
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2022-06-06 16:56:01 +00:00
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if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) {
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2023-11-28 19:30:39 +00:00
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m_memory.Write16(vaddr, value);
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}
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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void MemoryWrite32(u64 vaddr, u32 value) override {
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2022-06-06 16:56:01 +00:00
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if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) {
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2023-11-28 19:30:39 +00:00
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m_memory.Write32(vaddr, value);
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2022-06-06 16:56:01 +00:00
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}
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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void MemoryWrite64(u64 vaddr, u64 value) override {
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2022-06-06 16:56:01 +00:00
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if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) {
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2023-11-28 19:30:39 +00:00
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m_memory.Write64(vaddr, value);
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2022-06-06 16:56:01 +00:00
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}
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2018-01-09 21:33:46 +00:00
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}
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2018-02-09 00:04:05 +00:00
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void MemoryWrite128(u64 vaddr, Vector value) override {
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2022-06-06 16:56:01 +00:00
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if (CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write)) {
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2023-11-28 19:30:39 +00:00
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m_memory.Write64(vaddr, value[0]);
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m_memory.Write64(vaddr + 8, value[1]);
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2022-06-06 16:56:01 +00:00
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}
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2018-02-09 00:04:05 +00:00
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}
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2018-01-09 21:33:46 +00:00
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2020-03-07 22:59:42 +00:00
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bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
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2022-06-06 16:56:01 +00:00
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return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) &&
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2023-11-28 19:30:39 +00:00
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m_memory.WriteExclusive8(vaddr, value, expected);
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2020-03-07 22:59:42 +00:00
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}
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bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
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return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) &&
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2023-11-28 19:30:39 +00:00
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m_memory.WriteExclusive16(vaddr, value, expected);
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2020-03-07 22:59:42 +00:00
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}
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bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
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return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) &&
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2023-11-28 19:30:39 +00:00
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m_memory.WriteExclusive32(vaddr, value, expected);
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2020-03-07 22:59:42 +00:00
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}
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bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
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return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) &&
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2023-11-28 19:30:39 +00:00
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m_memory.WriteExclusive64(vaddr, value, expected);
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2020-03-07 22:59:42 +00:00
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}
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bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
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2022-06-06 16:56:01 +00:00
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return CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write) &&
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2023-11-28 19:30:39 +00:00
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m_memory.WriteExclusive128(vaddr, value, expected);
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2020-03-07 22:59:42 +00:00
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}
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2018-09-15 13:21:06 +00:00
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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2023-11-28 19:30:39 +00:00
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m_parent.LogBacktrace(m_process);
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2020-11-04 00:54:53 +00:00
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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2023-11-28 19:30:39 +00:00
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num_instructions, m_memory.Read32(pc));
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2023-06-13 01:34:25 +00:00
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ReturnException(pc, PrefetchAbort);
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2018-01-09 21:33:46 +00:00
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}
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2021-11-22 02:10:14 +00:00
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void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
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2023-03-18 01:26:04 +00:00
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u64 value) override {
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2021-11-22 02:10:14 +00:00
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switch (op) {
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2021-11-22 02:24:07 +00:00
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case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
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static constexpr u64 ICACHE_LINE_SIZE = 64;
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2021-11-22 02:10:14 +00:00
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2021-11-22 02:24:07 +00:00
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
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2023-11-28 19:30:39 +00:00
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m_parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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2021-11-22 02:24:07 +00:00
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break;
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}
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2021-11-22 02:10:14 +00:00
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
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2023-11-28 19:30:39 +00:00
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m_parent.ClearInstructionCache();
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2021-11-22 02:24:07 +00:00
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break;
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2021-11-22 02:10:14 +00:00
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
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default:
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2021-11-22 02:24:07 +00:00
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LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
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break;
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2021-11-22 02:10:14 +00:00
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}
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2022-03-27 14:37:19 +00:00
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2023-11-28 19:30:39 +00:00
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m_parent.m_jit->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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2021-11-22 02:10:14 +00:00
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}
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2018-02-09 00:04:05 +00:00
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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2022-06-21 00:39:16 +00:00
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case Dynarmic::A64::Exception::NoExecuteFault:
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LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#016x}", pc);
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2023-06-13 01:34:25 +00:00
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ReturnException(pc, PrefetchAbort);
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2022-06-21 00:39:16 +00:00
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return;
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
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default:
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2023-11-28 19:30:39 +00:00
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if (m_debugger_enabled) {
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2023-06-13 01:34:25 +00:00
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ReturnException(pc, InstructionBreakpoint);
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2022-05-30 23:35:01 +00:00
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return;
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}
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2023-11-28 19:30:39 +00:00
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m_parent.LogBacktrace(m_process);
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2022-06-21 00:39:16 +00:00
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LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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2023-11-28 19:30:39 +00:00
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static_cast<std::size_t>(exception), pc, m_memory.Read32(pc));
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
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}
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2018-01-13 22:34:15 +00:00
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}
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2023-11-28 19:30:39 +00:00
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void CallSVC(u32 svc) override {
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m_parent.m_svc = svc;
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m_parent.m_jit->HaltExecution(SupervisorCall);
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2018-01-09 21:33:46 +00:00
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}
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2018-01-13 22:34:15 +00:00
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void AddTicks(u64 ticks) override {
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2023-11-28 19:30:39 +00:00
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ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
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2020-11-04 00:54:53 +00:00
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2020-03-28 19:23:28 +00:00
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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2020-11-04 00:54:53 +00:00
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u64 amortized_ticks = ticks / Core::Hardware::NUM_CPU_CORES;
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2020-03-28 19:23:28 +00:00
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|
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// Always execute at least one tick.
|
|
|
|
amortized_ticks = std::max<u64>(amortized_ticks, 1);
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
m_parent.m_system.CoreTiming().AddTicks(amortized_ticks);
|
2018-01-09 21:33:46 +00:00
|
|
|
}
|
2020-03-20 16:36:01 +00:00
|
|
|
|
2018-01-13 22:34:15 +00:00
|
|
|
u64 GetTicksRemaining() override {
|
2023-11-28 19:30:39 +00:00
|
|
|
ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
|
2022-04-03 15:29:05 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
return std::max<s64>(m_parent.m_system.CoreTiming().GetDowncount(), 0);
|
2018-01-09 21:33:46 +00:00
|
|
|
}
|
2020-03-20 16:36:01 +00:00
|
|
|
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
|
|
|
u64 GetCNTPCT() override {
|
2023-11-28 19:30:39 +00:00
|
|
|
return m_parent.m_system.CoreTiming().GetClockTicks();
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
|
|
|
}
|
2018-01-09 21:33:46 +00:00
|
|
|
|
2023-03-18 01:26:04 +00:00
|
|
|
bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
|
2023-11-28 19:30:39 +00:00
|
|
|
if (!m_check_memory_access) {
|
2022-12-02 03:48:43 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
if (!m_memory.IsValidVirtualAddressRange(addr, size)) {
|
2022-12-02 03:48:43 +00:00
|
|
|
LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
|
|
|
|
addr);
|
2023-11-28 19:30:39 +00:00
|
|
|
m_parent.m_jit->HaltExecution(PrefetchAbort);
|
2022-12-02 03:48:43 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
if (!m_debugger_enabled) {
|
2022-06-06 16:56:01 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
const auto match{m_parent.MatchingWatchpoint(addr, size, type)};
|
2022-06-06 16:56:01 +00:00
|
|
|
if (match) {
|
2023-11-28 19:30:39 +00:00
|
|
|
m_parent.m_halted_watchpoint = match;
|
|
|
|
m_parent.m_jit->HaltExecution(DataAbort);
|
2022-06-06 16:56:01 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2022-06-21 00:39:16 +00:00
|
|
|
void ReturnException(u64 pc, Dynarmic::HaltReason hr) {
|
2023-11-28 19:30:39 +00:00
|
|
|
m_parent.GetContext(m_parent.m_breakpoint_context);
|
|
|
|
m_parent.m_breakpoint_context.pc = pc;
|
|
|
|
m_parent.m_jit->HaltExecution(hr);
|
2022-06-21 00:39:16 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
ArmDynarmic64& m_parent;
|
|
|
|
Core::Memory::Memory& m_memory;
|
|
|
|
u64 m_tpidrro_el0{};
|
|
|
|
u64 m_tpidr_el0{};
|
|
|
|
const Kernel::KProcess* m_process{};
|
|
|
|
const bool m_debugger_enabled{};
|
|
|
|
const bool m_check_memory_access{};
|
|
|
|
static constexpr u64 MinimumRunCycles = 10000U;
|
2018-01-09 21:33:46 +00:00
|
|
|
};
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
std::shared_ptr<Dynarmic::A64::Jit> ArmDynarmic64::MakeJit(Common::PageTable* page_table,
|
|
|
|
std::size_t address_space_bits) const {
|
2018-02-12 21:53:32 +00:00
|
|
|
Dynarmic::A64::UserConfig config;
|
2018-07-03 13:28:46 +00:00
|
|
|
|
|
|
|
// Callbacks
|
2023-11-28 19:30:39 +00:00
|
|
|
config.callbacks = m_cb.get();
|
2018-07-03 13:28:46 +00:00
|
|
|
|
|
|
|
// Memory
|
2021-03-24 11:08:41 +00:00
|
|
|
if (page_table) {
|
|
|
|
config.page_table = reinterpret_cast<void**>(page_table->pointers.data());
|
|
|
|
config.page_table_address_space_bits = address_space_bits;
|
|
|
|
config.page_table_pointer_mask_bits = Common::PageTable::ATTRIBUTE_BITS;
|
|
|
|
config.silently_mirror_page_table = false;
|
|
|
|
config.absolute_offset_page_table = true;
|
|
|
|
config.detect_misaligned_access_via_page_table = 16 | 32 | 64 | 128;
|
|
|
|
config.only_detect_misalignment_via_page_table_on_page_boundary = true;
|
2020-01-19 00:49:30 +00:00
|
|
|
|
|
|
|
config.fastmem_pointer = page_table->fastmem_arena;
|
|
|
|
config.fastmem_address_space_bits = address_space_bits;
|
|
|
|
config.silently_mirror_fastmem = false;
|
2022-02-27 19:40:05 +00:00
|
|
|
|
2022-08-09 19:48:19 +00:00
|
|
|
config.fastmem_exclusive_access = config.fastmem_pointer != nullptr;
|
2022-02-27 19:40:05 +00:00
|
|
|
config.recompile_on_exclusive_fastmem_failure = true;
|
2021-03-24 11:08:41 +00:00
|
|
|
}
|
2018-07-03 13:28:46 +00:00
|
|
|
|
|
|
|
// Multi-process state
|
2023-11-28 19:30:39 +00:00
|
|
|
config.processor_id = m_core_index;
|
|
|
|
config.global_monitor = &m_exclusive_monitor.monitor;
|
2018-07-03 13:28:46 +00:00
|
|
|
|
|
|
|
// System registers
|
2023-11-28 19:30:39 +00:00
|
|
|
config.tpidrro_el0 = &m_cb->m_tpidrro_el0;
|
|
|
|
config.tpidr_el0 = &m_cb->m_tpidr_el0;
|
2018-02-12 21:53:32 +00:00
|
|
|
config.dczid_el0 = 4;
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
|
|
|
config.ctr_el0 = 0x8444c004;
|
2020-02-11 23:56:24 +00:00
|
|
|
config.cntfrq_el0 = Hardware::CNTFREQ;
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 20:51:54 +00:00
|
|
|
|
2018-08-16 09:12:20 +00:00
|
|
|
// Unpredictable instructions
|
|
|
|
config.define_unpredictable_behaviour = true;
|
|
|
|
|
2020-05-03 02:03:09 +00:00
|
|
|
// Timing
|
2023-11-28 19:30:39 +00:00
|
|
|
config.wall_clock_cntpct = m_uses_wall_clock;
|
|
|
|
config.enable_cycle_counting = !m_uses_wall_clock;
|
2020-03-21 16:23:13 +00:00
|
|
|
|
2021-04-02 17:08:39 +00:00
|
|
|
// Code cache size
|
2023-01-05 23:06:06 +00:00
|
|
|
#ifdef ARCHITECTURE_arm64
|
|
|
|
config.code_cache_size = 128_MiB;
|
|
|
|
#else
|
2022-03-23 01:32:54 +00:00
|
|
|
config.code_cache_size = 512_MiB;
|
2023-01-05 23:06:06 +00:00
|
|
|
#endif
|
2021-04-02 17:08:39 +00:00
|
|
|
|
2022-06-06 16:56:01 +00:00
|
|
|
// Allow memory fault handling to work
|
2023-11-28 19:30:39 +00:00
|
|
|
if (m_system.DebuggerEnabled()) {
|
2022-06-06 16:56:01 +00:00
|
|
|
config.check_halt_on_memory_access = true;
|
|
|
|
}
|
|
|
|
|
2022-04-10 14:46:29 +00:00
|
|
|
// null_jit
|
|
|
|
if (!page_table) {
|
|
|
|
// Don't waste too much memory on null_jit
|
|
|
|
config.code_cache_size = 8_MiB;
|
|
|
|
}
|
|
|
|
|
2020-07-11 13:26:36 +00:00
|
|
|
// Safe optimizations
|
2021-07-08 20:56:44 +00:00
|
|
|
if (Settings::values.cpu_debug_mode) {
|
2020-07-11 15:25:49 +00:00
|
|
|
if (!Settings::values.cpuopt_page_tables) {
|
|
|
|
config.page_table = nullptr;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_block_linking) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::BlockLinking;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_return_stack_buffer) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::ReturnStackBuffer;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_fast_dispatcher) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::FastDispatch;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_context_elimination) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::GetSetElimination;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_const_prop) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::ConstProp;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_misc_ir) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::MiscIROpt;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_reduce_misalign_checks) {
|
|
|
|
config.only_detect_misalignment_via_page_table_on_page_boundary = false;
|
|
|
|
}
|
2021-06-06 07:57:24 +00:00
|
|
|
if (!Settings::values.cpuopt_fastmem) {
|
|
|
|
config.fastmem_pointer = nullptr;
|
2022-08-09 19:48:19 +00:00
|
|
|
config.fastmem_exclusive_access = false;
|
2021-06-06 07:57:24 +00:00
|
|
|
}
|
2022-02-27 19:40:05 +00:00
|
|
|
if (!Settings::values.cpuopt_fastmem_exclusives) {
|
|
|
|
config.fastmem_exclusive_access = false;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_recompile_exclusives) {
|
|
|
|
config.recompile_on_exclusive_fastmem_failure = false;
|
|
|
|
}
|
2022-12-02 03:48:43 +00:00
|
|
|
if (!Settings::values.cpuopt_ignore_memory_aborts) {
|
|
|
|
config.check_halt_on_memory_access = true;
|
|
|
|
}
|
2022-03-26 08:45:51 +00:00
|
|
|
} else {
|
|
|
|
// Unsafe optimizations
|
2023-06-07 05:52:23 +00:00
|
|
|
if (Settings::values.cpu_accuracy.GetValue() == Settings::CpuAccuracy::Unsafe) {
|
2022-03-26 08:45:51 +00:00
|
|
|
config.unsafe_optimizations = true;
|
|
|
|
if (Settings::values.cpuopt_unsafe_unfuse_fma) {
|
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
|
|
|
|
}
|
|
|
|
if (Settings::values.cpuopt_unsafe_reduce_fp_error) {
|
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_ReducedErrorFP;
|
|
|
|
}
|
|
|
|
if (Settings::values.cpuopt_unsafe_inaccurate_nan) {
|
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_InaccurateNaN;
|
|
|
|
}
|
|
|
|
if (Settings::values.cpuopt_unsafe_fastmem_check) {
|
|
|
|
config.fastmem_address_space_bits = 64;
|
|
|
|
}
|
|
|
|
if (Settings::values.cpuopt_unsafe_ignore_global_monitor) {
|
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_IgnoreGlobalMonitor;
|
|
|
|
}
|
|
|
|
}
|
2020-07-11 13:26:36 +00:00
|
|
|
|
2022-03-26 08:45:51 +00:00
|
|
|
// Curated optimizations
|
2023-06-07 05:52:23 +00:00
|
|
|
if (Settings::values.cpu_accuracy.GetValue() == Settings::CpuAccuracy::Auto) {
|
2022-03-26 08:45:51 +00:00
|
|
|
config.unsafe_optimizations = true;
|
2020-08-16 12:19:55 +00:00
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
|
2021-07-01 02:22:21 +00:00
|
|
|
config.fastmem_address_space_bits = 64;
|
2022-02-27 19:40:05 +00:00
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_IgnoreGlobalMonitor;
|
|
|
|
}
|
2021-07-01 02:22:21 +00:00
|
|
|
|
2022-03-26 08:45:51 +00:00
|
|
|
// Paranoia mode for debugging optimizations
|
2023-06-07 05:52:23 +00:00
|
|
|
if (Settings::values.cpu_accuracy.GetValue() == Settings::CpuAccuracy::Paranoid) {
|
2022-03-26 08:45:51 +00:00
|
|
|
config.unsafe_optimizations = false;
|
|
|
|
config.optimizations = Dynarmic::no_optimizations;
|
|
|
|
}
|
2020-08-16 12:19:55 +00:00
|
|
|
}
|
|
|
|
|
2020-02-26 19:53:47 +00:00
|
|
|
return std::make_shared<Dynarmic::A64::Jit>(config);
|
2018-02-09 00:04:05 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
HaltReason ArmDynarmic64::RunThread(Kernel::KThread* thread) {
|
|
|
|
m_jit->ClearExclusiveState();
|
|
|
|
return TranslateHaltReason(m_jit->Run());
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
HaltReason ArmDynarmic64::StepThread(Kernel::KThread* thread) {
|
|
|
|
m_jit->ClearExclusiveState();
|
|
|
|
return TranslateHaltReason(m_jit->Step());
|
2022-04-21 00:17:48 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
u32 ArmDynarmic64::GetSvcNumber() const {
|
|
|
|
return m_svc;
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::GetSvcArguments(std::span<uint64_t, 8> args) const {
|
|
|
|
Dynarmic::A64::Jit& j = *m_jit;
|
2016-09-02 03:07:14 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
for (size_t i = 0; i < 8; i++) {
|
|
|
|
args[i] = j.GetRegister(i);
|
|
|
|
}
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::SetSvcArguments(std::span<const uint64_t, 8> args) {
|
|
|
|
Dynarmic::A64::Jit& j = *m_jit;
|
2016-09-02 03:07:14 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
for (size_t i = 0; i < 8; i++) {
|
|
|
|
j.SetRegister(i, args[i]);
|
|
|
|
}
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
const Kernel::DebugWatchpoint* ArmDynarmic64::HaltedWatchpoint() const {
|
|
|
|
return m_halted_watchpoint;
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::RewindBreakpointInstruction() {
|
|
|
|
this->SetContext(m_breakpoint_context);
|
2017-09-30 18:16:39 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
ArmDynarmic64::ArmDynarmic64(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
|
|
|
|
DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index)
|
|
|
|
: ArmInterface{uses_wall_clock}, m_system{system}, m_exclusive_monitor{exclusive_monitor},
|
|
|
|
m_cb(std::make_unique<DynarmicCallbacks64>(*this, process)), m_core_index{core_index} {
|
|
|
|
auto& page_table = process->GetPageTable().GetBasePageTable();
|
|
|
|
auto& page_table_impl = page_table.GetImpl();
|
|
|
|
m_jit = MakeJit(&page_table_impl, page_table.GetAddressSpaceWidth());
|
2017-09-30 18:16:39 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
ArmDynarmic64::~ArmDynarmic64() = default;
|
2018-07-21 00:57:45 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::SetTpidrroEl0(u64 value) {
|
|
|
|
m_cb->m_tpidrro_el0 = value;
|
2018-07-21 00:57:45 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::GetContext(Kernel::Svc::ThreadContext& ctx) const {
|
|
|
|
Dynarmic::A64::Jit& j = *m_jit;
|
|
|
|
auto gpr = j.GetRegisters();
|
|
|
|
auto fpr = j.GetVectors();
|
2016-09-02 03:07:14 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
// TODO: this is inconvenient
|
|
|
|
for (size_t i = 0; i < 29; i++) {
|
|
|
|
ctx.r[i] = gpr[i];
|
|
|
|
}
|
|
|
|
ctx.fp = gpr[29];
|
|
|
|
ctx.lr = gpr[30];
|
|
|
|
|
|
|
|
ctx.sp = j.GetSP();
|
|
|
|
ctx.pc = j.GetPC();
|
|
|
|
ctx.pstate = j.GetPstate();
|
|
|
|
ctx.v = fpr;
|
|
|
|
ctx.fpcr = j.GetFpcr();
|
|
|
|
ctx.fpsr = j.GetFpsr();
|
|
|
|
ctx.tpidr = m_cb->m_tpidr_el0;
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::SetContext(const Kernel::Svc::ThreadContext& ctx) {
|
|
|
|
Dynarmic::A64::Jit& j = *m_jit;
|
2016-09-02 03:07:14 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
// TODO: this is inconvenient
|
|
|
|
std::array<u64, 31> gpr;
|
2022-07-08 00:06:46 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
for (size_t i = 0; i < 29; i++) {
|
|
|
|
gpr[i] = ctx.r[i];
|
|
|
|
}
|
|
|
|
gpr[29] = ctx.fp;
|
|
|
|
gpr[30] = ctx.lr;
|
|
|
|
|
|
|
|
j.SetRegisters(gpr);
|
|
|
|
j.SetSP(ctx.sp);
|
|
|
|
j.SetPC(ctx.pc);
|
|
|
|
j.SetPstate(ctx.pstate);
|
|
|
|
j.SetVectors(ctx.v);
|
|
|
|
j.SetFpcr(ctx.fpcr);
|
|
|
|
j.SetFpsr(ctx.fpsr);
|
|
|
|
m_cb->m_tpidr_el0 = ctx.tpidr;
|
2016-09-02 03:07:14 +00:00
|
|
|
}
|
2017-09-24 21:44:13 +00:00
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::SignalInterrupt(Kernel::KThread* thread) {
|
|
|
|
m_jit->HaltExecution(BreakLoop);
|
2020-11-14 07:20:32 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::ClearInstructionCache() {
|
|
|
|
m_jit->ClearCache();
|
2018-07-16 10:24:00 +00:00
|
|
|
}
|
|
|
|
|
2023-11-28 19:30:39 +00:00
|
|
|
void ArmDynarmic64::InvalidateCacheRange(u64 addr, std::size_t size) {
|
|
|
|
m_jit->InvalidateCacheRange(addr, size);
|
2017-09-24 21:44:13 +00:00
|
|
|
}
|
2018-07-03 13:28:46 +00:00
|
|
|
|
2018-08-25 01:43:32 +00:00
|
|
|
} // namespace Core
|