765e304c4b
```sh
git grep -l '^patch_args=-Np0' "srcpkgs/$1*/template" |
while read template; do
for p in ${template%/template}/patches/*; do
sed -i '
\,^[+-][+-][+-] /dev/null,b
/^[*-]\+ [0-9]\+\(,[0-9]\+\)\? [*-]\+$/b
s,^[*][*][*] ,&a/,
/^--- /{
s,\(^--- \)\(./\)*,\1a/,
s,[.][Oo][Rr][Ii][Gg]\([ /]\),\1,
s/[.][Oo][Rr][Ii][Gg]$//
s/[.]patched[.]\([^.]\)/.\1/
h
}
/^+++ -/{
g
s/^--- a/+++ b/
b
}
s,\(^+++ \)\(./\)*,\1b/,
' "$p"
done
sed -i '/^patch_args=/d' $template
done
```
101 lines
2.8 KiB
Diff
101 lines
2.8 KiB
Diff
Patch to get memtest86+ working with gcc 4.7.2 or later and PCI scan fix
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these patches were taken from Mageia
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upstream report containing link to the patches:
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http://forum.canardpc.com/threads/83443-Memtest86-V5.01-crashes-with-gcc-4.7.2-or-later
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Patch source: http://pkgs.fedoraproject.org/cgit/rpms/memtest86+.git/
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--- a/controller.c
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+++ b/controller.c
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@@ -2,6 +2,8 @@
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* MemTest86+ V5 Specific code (GPL V2.0)
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* By Samuel DEMEULEMEESTER, sdemeule@memtest.org
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* http://www.canardpc.com - http://www.memtest.org
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+ *
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+ * Edited by David McInnis Oct 4, 2014
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*/
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//#include "defs.h"
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@@ -292,7 +294,7 @@ static void setup_nhm(void)
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/* First, locate the PCI bus where the MCH is located */
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- for(i = 0; i < sizeof(possible_nhm_bus); i++) {
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+ for(i = 0; i < sizeof(possible_nhm_bus) / sizeof(possible_nhm_bus[0]); i++) {
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pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
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pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
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vid &= 0xFFFF;
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@@ -327,7 +329,7 @@ static void setup_nhm32(void)
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ctrl.mode = ECC_NONE;
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/* First, locate the PCI bus where the MCH is located */
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- for(i = 0; i < sizeof(possible_nhm_bus); i++) {
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+ for(i = 0; i < sizeof(possible_nhm_bus) / sizeof(possible_nhm_bus[0]); i++) {
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pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
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pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
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vid &= 0xFFFF;
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@@ -1424,7 +1426,7 @@ static void poll_fsb_amd64(void) {
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unsigned long dramchr;
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float clockratio;
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double dramclock;
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- unsigned int dummy[3];
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+ unsigned int dummy[4];
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int ram_type;
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float coef = 10;
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@@ -2851,13 +2853,13 @@ static void poll_timings_nf4ie(void) {
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static void poll_timings_i875(void) {
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- ulong dev6, dev62;
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+ ulong dev6;
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ulong temp;
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float cas;
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int rcd, rp, ras, chan;
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long *ptr, *ptr2;
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- pci_conf_read( 0, 6, 0, 0x40, 4, &dev62);
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+ pci_conf_read( 0, 6, 0, 0x40, 4, &dev6);
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ptr2=(long*)(dev6+0x68);
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/* Read the MMR Base Address & Define the pointer */
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--- a/init.c
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+++ b/init.c
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@@ -7,6 +7,8 @@
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*
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* Released under version 2 of the Gnu Public License.
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* By Chris Brady
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+ *
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+ * Edited by David McInnis October 4, 2014
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*/
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@@ -914,7 +916,6 @@ void cpu_type(void)
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default:
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cprint(0, COL_MID, "Unknown Intel");
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break;
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- break;
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}
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}
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--- a/main.c
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+++ b/main.c
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@@ -422,7 +422,7 @@ void test_start(void)
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//initialise_cpus();
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btrace(my_cpu_num, __LINE__, "BeforeInit", 1, 0, 0);
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/* Draw the screen and get system information */
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- init();
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+ init();
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/* Set defaults and initialize variables */
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set_defaults();
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@@ -737,7 +737,7 @@ void test_start(void)
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/* Do the same test for each CPU */
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if (++cpu_sel >= act_cpus)
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{
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- cpu_sel = 0;
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+ cpu_sel = 0;
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next_test();
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} else {
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continue;
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