80 lines
3 KiB
Diff
80 lines
3 KiB
Diff
From 0539bf1adfbbb04db0eda74e487fb16d7c5f8570 Mon Sep 17 00:00:00 2001
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From: Daniel Kolesa <daniel@octaforge.org>
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Date: Wed, 29 Apr 2020 16:51:37 +0200
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Subject: [PATCH] drm/amd/display: work around fp code being emitted outside of
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DC_FP_START/END
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The dcn20_validate_bandwidth function would have code touching the
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incorrect registers emitted outside of the boundaries of the
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DC_FP_START/END macros, at least on ppc64le. Work around the
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problem by wrapping the whole function instead.
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Signed-off-by: Daniel Kolesa <daniel@octaforge.org>
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---
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.../drm/amd/display/dc/dcn20/dcn20_resource.c | 31 ++++++++++++++-----
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1 file changed, 23 insertions(+), 8 deletions(-)
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diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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index e310d67..1b0bca9 100644
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--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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@@ -3034,25 +3034,32 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
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return out;
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}
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-
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-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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- bool fast_validate)
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+/*
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+ * This must be noinline to ensure anything that deals with FP registers
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+ * is contained within this call; previously our compiling with hard-float
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+ * would result in fp instructions being emitted outside of the boundaries
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+ * of the DC_FP_START/END macros, which makes sense as the compiler has no
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+ * idea about what is wrapped and what is not
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+ *
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+ * This is largely just a workaround to avoid breakage introduced with 5.6,
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+ * ideally all fp-using code should be moved into its own file, only that
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+ * should be compiled with hard-float, and all code exported from there
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+ * should be strictly wrapped with DC_FP_START/END
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+ */
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+static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
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+ struct dc_state *context, bool fast_validate)
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{
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bool voltage_supported = false;
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bool full_pstate_supported = false;
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bool dummy_pstate_supported = false;
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double p_state_latency_us;
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- DC_FP_START();
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p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
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context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
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dc->debug.disable_dram_clock_change_vactive_support;
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if (fast_validate) {
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- voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
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-
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- DC_FP_END();
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- return voltage_supported;
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+ return dcn20_validate_bandwidth_internal(dc, context, true);
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}
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// Best case, we support full UCLK switch latency
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@@ -3081,7 +3088,15 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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restore_dml_state:
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context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
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+ return voltage_supported;
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+}
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+bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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+ bool fast_validate)
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+{
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+ bool voltage_supported = false;
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+ DC_FP_START();
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+ voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
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DC_FP_END();
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return voltage_supported;
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}
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--
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2.26.2
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