102 lines
3 KiB
Diff
102 lines
3 KiB
Diff
GCC's version of __builtin___clear_cache() is a no-op on PowerPC.
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Change to use an improved version of the existing ppc_cache_flush().
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--- a/sljit/sljitConfigInternal.h 2022-02-12 21:42:26.812059103 -0800
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+++ b/sljit/sljitConfigInternal.h 2022-02-12 21:42:57.508834803 -0800
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@@ -284,7 +284,8 @@
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/****************************/
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#if (!defined SLJIT_CACHE_FLUSH && defined __has_builtin)
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-#if __has_builtin(__builtin___clear_cache)
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+#if __has_builtin(__builtin___clear_cache) && \
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+ !(defined SLJIT_CONFIG_PPC && SLJIT_CONFIG_PPC)
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#define SLJIT_CACHE_FLUSH(from, to) \
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__builtin___clear_cache((char*)from, (char*)to)
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--- a/sljit/sljitNativePPC_common.c 2022-02-12 21:42:26.816059204 -0800
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+++ b/sljit/sljitNativePPC_common.c 2022-02-12 21:42:57.512834904 -0800
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@@ -46,6 +46,39 @@
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#define SLJIT_PASS_ENTRY_ADDR_TO_CALL 1
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#endif
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+#ifdef __linux__
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+#include <sys/auxv.h>
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+
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+/* Return the instruction cache line size, in bytes. */
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+static SLJIT_INLINE sljit_u32 get_icache_line_size()
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+{
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+ static sljit_u32 icache_line_size = 0;
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+ if (SLJIT_UNLIKELY(!icache_line_size)) {
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+ icache_line_size = (sljit_u32) getauxval(AT_ICACHEBSIZE);
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+ SLJIT_ASSERT(icache_line_size != 0);
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+ }
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+ return icache_line_size;
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+}
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+
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+/* Cache and return the first hardware capabilities word. */
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+static SLJIT_INLINE unsigned long get_hwcap()
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+{
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+ static unsigned long hwcap = 0;
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+ if (SLJIT_UNLIKELY(!hwcap)) {
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+ hwcap = getauxval(AT_HWCAP);
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+ SLJIT_ASSERT(hwcap != 0);
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+ }
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+ return hwcap;
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+}
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+
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+/* Return non-zero if this CPU has the icache snoop feature. */
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+static SLJIT_INLINE unsigned long has_feature_icache_snoop()
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+{
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+ return (get_hwcap() & PPC_FEATURE_ICACHE_SNOOP);
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+}
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+
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+#endif /* __linux__ */
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+
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#if (defined SLJIT_CACHE_FLUSH_OWN_IMPL && SLJIT_CACHE_FLUSH_OWN_IMPL)
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static void ppc_cache_flush(sljit_ins *from, sljit_ins *to)
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@@ -68,14 +101,40 @@
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# error "Cache flush is not implemented for PowerPC/POWER common mode."
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# else
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/* Cache flush for PowerPC architecture. */
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- while (from < to) {
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+ /* For POWER5 and up with icache snooping, only one icbi in the range
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+ * is required. The sync flushes the store queue, and the icbi/isync
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+ * kills the local prefetch.
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+ */
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+ if (has_feature_icache_snoop()) {
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__asm__ volatile (
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- "dcbf 0, %0\n"
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"sync\n"
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"icbi 0, %0\n"
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- : : "r"(from)
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+ "isync\n"
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+ : : "r"(from) : "memory"
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+ );
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+ return;
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+ }
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+
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+ sljit_u32 cache_line_bytes = get_icache_line_size();
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+ sljit_u32 cache_line_words = cache_line_bytes / sizeof(sljit_ins);
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+ uintptr_t cache_line_mask = ~(uintptr_t)(cache_line_bytes - 1);
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+
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+ /* Round down to start of cache line to simplify the end condition. */
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+ sljit_ins* start = (sljit_ins*)((uintptr_t)(from) & cache_line_mask);
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+
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+ for (from = start; from < to; from += cache_line_words) {
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+ __asm__ volatile (
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+ "dcbf 0, %0"
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+ : : "r"(from) : "memory"
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+ );
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+ }
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+ __asm__ volatile ( "sync" );
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+
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+ for (from = start; from < to; from += cache_line_words) {
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+ __asm__ volatile (
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+ "icbi 0, %0"
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+ : : "r"(from) : "memory"
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);
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- from++;
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}
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__asm__ volatile ( "isync" );
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# endif
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