gcc: update to 9.3.0.
This commit is contained in:
Juan RP
parent
964803abff
commit
70ed4c73c6
3 changed files with 5 additions and 526 deletions
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@ -1,504 +0,0 @@
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Upstream: yes
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Reference: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91481
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https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=275170
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https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=275181
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Fixes a security issue with the hardware random number generator
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when compiling for POWER9. Since Void compiles for POWER8 by
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default, it's not affected, but people building custom binaries
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might be.
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--- gcc/config/rs6000/altivec.md
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+++ gcc/config/rs6000/altivec.md
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@@ -80,9 +80,6 @@
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UNSPEC_VUPKHPX
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UNSPEC_VUPKLPX
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UNSPEC_CONVERT_4F32_8I16
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- UNSPEC_DARN
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- UNSPEC_DARN_32
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- UNSPEC_DARN_RAW
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UNSPEC_DST
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UNSPEC_DSTT
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UNSPEC_DSTST
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@@ -161,9 +158,6 @@
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UNSPEC_BCDADD
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UNSPEC_BCDSUB
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UNSPEC_BCD_OVERFLOW
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- UNSPEC_CMPRB
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- UNSPEC_CMPRB2
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- UNSPEC_CMPEQB
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UNSPEC_VRLMI
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UNSPEC_VRLNM
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])
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@@ -4101,223 +4095,6 @@
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"bcd<bcd_add_sub>. %0,%1,%2,%3"
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[(set_attr "type" "vecsimple")])
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-(define_insn "darn_32"
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- [(set (match_operand:SI 0 "register_operand" "=r")
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- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
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- "TARGET_P9_MISC"
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- "darn %0,0"
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- [(set_attr "type" "integer")])
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-
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-(define_insn "darn_raw"
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- [(set (match_operand:DI 0 "register_operand" "=r")
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- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
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- "TARGET_P9_MISC && TARGET_64BIT"
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- "darn %0,2"
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- [(set_attr "type" "integer")])
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-
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-(define_insn "darn"
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- [(set (match_operand:DI 0 "register_operand" "=r")
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- (unspec:DI [(const_int 0)] UNSPEC_DARN))]
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- "TARGET_P9_MISC && TARGET_64BIT"
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- "darn %0,1"
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- [(set_attr "type" "integer")])
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-
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-;; Test byte within range.
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-;;
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the range specified by operand 2.
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-;; The bytes of operand 2 are organized as xx:xx:hi:lo.
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-;;
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-;; Return in target register operand 0 a value of 1 if lo <= vv and
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-;; vv <= hi. Otherwise, set register operand 0 to 0.
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-;;
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-;; Though the instructions to which this expansion maps operate on
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-;; 64-bit registers, the current implementation only operates on
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-;; SI-mode operands as the high-order bits provide no information
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-;; that is not already available in the low-order bits. To avoid the
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-;; costs of data widening operations, future enhancements might allow
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-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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-(define_expand "cmprb"
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- [(set (match_dup 3)
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB))
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- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_dup 3)
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 3)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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-{
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- operands[3] = gen_reg_rtx (CCmode);
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-})
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-
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the range specified by operand 2.
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-;; The bytes of operand 2 are organized as xx:xx:hi:lo.
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-;;
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-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
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-;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
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-;; 3 bits of the target CR register are all set to 0.
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-(define_insn "*cmprb_internal"
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- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB))]
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- "TARGET_P9_MISC"
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- "cmprb %0,0,%1,%2"
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- [(set_attr "type" "logical")])
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-
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-;; Set operand 0 register to -1 if the LT bit (0x8) of condition
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-;; register operand 1 is on. Otherwise, set operand 0 register to 1
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-;; if the GT bit (0x4) of condition register operand 1 is on.
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-;; Otherwise, set operand 0 to 0. Note that the result stored into
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-;; register operand 0 is non-zero iff either the LT or GT bits are on
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-;; within condition register operand 1.
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-(define_insn "setb_signed"
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- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 1)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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- "setb %0,%1"
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- [(set_attr "type" "logical")])
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-
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-(define_insn "setb_unsigned"
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- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gtu (match_dup 1)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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- "setb %0,%1"
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- [(set_attr "type" "logical")])
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-
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-;; Test byte within two ranges.
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-;;
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the range specified by operand 2.
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-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
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-;;
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-;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
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-;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
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-;; operand 0 to 0.
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-;;
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-;; Though the instructions to which this expansion maps operate on
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-;; 64-bit registers, the current implementation only operates on
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-;; SI-mode operands as the high-order bits provide no information
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-;; that is not already available in the low-order bits. To avoid the
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-;; costs of data widening operations, future enhancements might allow
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-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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-(define_expand "cmprb2"
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- [(set (match_dup 3)
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB2))
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- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_dup 3)
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 3)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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-{
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- operands[3] = gen_reg_rtx (CCmode);
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-})
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-
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the ranges specified by operand 2.
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-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
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-;;
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-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
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-;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
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-;; Otherwise, set the GT bit to 0. The other 3 bits of the target
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-;; CR register are all set to 0.
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-(define_insn "*cmprb2_internal"
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- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB2))]
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- "TARGET_P9_MISC"
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- "cmprb %0,1,%1,%2"
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- [(set_attr "type" "logical")])
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-
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-;; Test byte membership within set of 8 bytes.
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-;;
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the set specified by operand 2.
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-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
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-;;
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-;; Return in target register operand 0 a value of 1 if vv equals one
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-;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
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-;; register operand 0 to 0. Note that the 8 byte values held within
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-;; operand 2 need not be unique.
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-;;
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-;; Though the instructions to which this expansion maps operate on
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-;; 64-bit registers, the current implementation requires that operands
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-;; 0 and 1 have mode SI as the high-order bits provide no information
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-;; that is not already available in the low-order bits. To avoid the
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-;; costs of data widening operations, future enhancements might allow
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-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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-(define_expand "cmpeqb"
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- [(set (match_dup 3)
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:DI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPEQB))
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- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_dup 3)
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 3)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC && TARGET_64BIT"
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-{
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- operands[3] = gen_reg_rtx (CCmode);
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-})
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-
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the set specified by operand 2.
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-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
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-;;
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-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
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-;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
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-;; set the GT bit to zero. The other 3 bits of the target CR register
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-;; are all set to 0.
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-(define_insn "*cmpeqb_internal"
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- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:DI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPEQB))]
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- "TARGET_P9_MISC && TARGET_64BIT"
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- "cmpeqb %0,%1,%2"
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- [(set_attr "type" "logical")])
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-
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(define_expand "bcd<bcd_add_sub>_<code>"
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[(parallel [(set (reg:CCFP CR6_REGNO)
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(compare:CCFP
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--- gcc/config/rs6000/rs6000.md
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+++ gcc/config/rs6000/rs6000.md
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@@ -137,6 +137,9 @@
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UNSPEC_LSQ
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UNSPEC_FUSION_GPR
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UNSPEC_STACK_CHECK
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+ UNSPEC_CMPRB
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+ UNSPEC_CMPRB2
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+ UNSPEC_CMPEQB
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UNSPEC_ADD_ROUND_TO_ODD
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UNSPEC_SUB_ROUND_TO_ODD
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UNSPEC_MUL_ROUND_TO_ODD
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@@ -164,6 +167,9 @@
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UNSPECV_EH_RR ; eh_reg_restore
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UNSPECV_ISYNC ; isync instruction
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UNSPECV_MFTB ; move from time base
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+ UNSPECV_DARN ; darn 1 (deliver a random number)
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+ UNSPECV_DARN_32 ; darn 2
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+ UNSPECV_DARN_RAW ; darn 0
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UNSPECV_NLGR ; non-local goto receiver
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UNSPECV_MFFS ; Move from FPSCR
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UNSPECV_MFFSL ; Move from FPSCR light instruction version
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@@ -13853,6 +13859,224 @@
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[(set_attr "type" "vecmove")
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(set_attr "size" "128")])
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+;; Miscellaneous ISA 3.0 (power9) instructions
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+
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+(define_insn "darn_32"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
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+ "TARGET_P9_MISC"
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+ "darn %0,0"
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+ [(set_attr "type" "integer")])
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+
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+(define_insn "darn_raw"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
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+ "TARGET_P9_MISC && TARGET_64BIT"
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+ "darn %0,2"
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+ [(set_attr "type" "integer")])
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+
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+(define_insn "darn"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
|
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+ "TARGET_P9_MISC && TARGET_64BIT"
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+ "darn %0,1"
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+ [(set_attr "type" "integer")])
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+
|
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+;; Test byte within range.
|
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+;;
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||||
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
+;; represents a byte whose value is ignored in this context and
|
||||
+;; vv, the least significant byte, holds the byte value that is to
|
||||
+;; be tested for membership within the range specified by operand 2.
|
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+;; The bytes of operand 2 are organized as xx:xx:hi:lo.
|
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+;;
|
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+;; Return in target register operand 0 a value of 1 if lo <= vv and
|
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+;; vv <= hi. Otherwise, set register operand 0 to 0.
|
||||
+;;
|
||||
+;; Though the instructions to which this expansion maps operate on
|
||||
+;; 64-bit registers, the current implementation only operates on
|
||||
+;; SI-mode operands as the high-order bits provide no information
|
||||
+;; that is not already available in the low-order bits. To avoid the
|
||||
+;; costs of data widening operations, future enhancements might allow
|
||||
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||
+(define_expand "cmprb"
|
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+ [(set (match_dup 3)
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+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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+ (match_operand:SI 2 "gpc_reg_operand" "r")]
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+ UNSPEC_CMPRB))
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+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
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||||
+ (if_then_else:SI (lt (match_dup 3)
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+ (const_int 0))
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+ (const_int -1)
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+ (if_then_else (gt (match_dup 3)
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||||
+ (const_int 0))
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+ (const_int 1)
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+ (const_int 0))))]
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+ "TARGET_P9_MISC"
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+{
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+ operands[3] = gen_reg_rtx (CCmode);
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+})
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+
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+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
+;; represents a byte whose value is ignored in this context and
|
||||
+;; vv, the least significant byte, holds the byte value that is to
|
||||
+;; be tested for membership within the range specified by operand 2.
|
||||
+;; The bytes of operand 2 are organized as xx:xx:hi:lo.
|
||||
+;;
|
||||
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
|
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+;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
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+;; 3 bits of the target CR register are all set to 0.
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+(define_insn "*cmprb_internal"
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+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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+ (match_operand:SI 2 "gpc_reg_operand" "r")]
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+ UNSPEC_CMPRB))]
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+ "TARGET_P9_MISC"
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+ "cmprb %0,0,%1,%2"
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+ [(set_attr "type" "logical")])
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+
|
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+;; Set operand 0 register to -1 if the LT bit (0x8) of condition
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||||
+;; register operand 1 is on. Otherwise, set operand 0 register to 1
|
||||
+;; if the GT bit (0x4) of condition register operand 1 is on.
|
||||
+;; Otherwise, set operand 0 to 0. Note that the result stored into
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||||
+;; register operand 0 is non-zero iff either the LT or GT bits are on
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||||
+;; within condition register operand 1.
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+(define_insn "setb_signed"
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+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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||||
+ (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
|
||||
+ (const_int 0))
|
||||
+ (const_int -1)
|
||||
+ (if_then_else (gt (match_dup 1)
|
||||
+ (const_int 0))
|
||||
+ (const_int 1)
|
||||
+ (const_int 0))))]
|
||||
+ "TARGET_P9_MISC"
|
||||
+ "setb %0,%1"
|
||||
+ [(set_attr "type" "logical")])
|
||||
+
|
||||
+(define_insn "setb_unsigned"
|
||||
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
+ (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
|
||||
+ (const_int 0))
|
||||
+ (const_int -1)
|
||||
+ (if_then_else (gtu (match_dup 1)
|
||||
+ (const_int 0))
|
||||
+ (const_int 1)
|
||||
+ (const_int 0))))]
|
||||
+ "TARGET_P9_MISC"
|
||||
+ "setb %0,%1"
|
||||
+ [(set_attr "type" "logical")])
|
||||
+
|
||||
+;; Test byte within two ranges.
|
||||
+;;
|
||||
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
+;; represents a byte whose value is ignored in this context and
|
||||
+;; vv, the least significant byte, holds the byte value that is to
|
||||
+;; be tested for membership within the range specified by operand 2.
|
||||
+;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
|
||||
+;;
|
||||
+;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
|
||||
+;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
|
||||
+;; operand 0 to 0.
|
||||
+;;
|
||||
+;; Though the instructions to which this expansion maps operate on
|
||||
+;; 64-bit registers, the current implementation only operates on
|
||||
+;; SI-mode operands as the high-order bits provide no information
|
||||
+;; that is not already available in the low-order bits. To avoid the
|
||||
+;; costs of data widening operations, future enhancements might allow
|
||||
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||
+(define_expand "cmprb2"
|
||||
+ [(set (match_dup 3)
|
||||
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||
+ UNSPEC_CMPRB2))
|
||||
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
+ (if_then_else:SI (lt (match_dup 3)
|
||||
+ (const_int 0))
|
||||
+ (const_int -1)
|
||||
+ (if_then_else (gt (match_dup 3)
|
||||
+ (const_int 0))
|
||||
+ (const_int 1)
|
||||
+ (const_int 0))))]
|
||||
+ "TARGET_P9_MISC"
|
||||
+{
|
||||
+ operands[3] = gen_reg_rtx (CCmode);
|
||||
+})
|
||||
+
|
||||
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
+;; represents a byte whose value is ignored in this context and
|
||||
+;; vv, the least significant byte, holds the byte value that is to
|
||||
+;; be tested for membership within the ranges specified by operand 2.
|
||||
+;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
|
||||
+;;
|
||||
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
|
||||
+;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
|
||||
+;; Otherwise, set the GT bit to 0. The other 3 bits of the target
|
||||
+;; CR register are all set to 0.
|
||||
+(define_insn "*cmprb2_internal"
|
||||
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||
+ UNSPEC_CMPRB2))]
|
||||
+ "TARGET_P9_MISC"
|
||||
+ "cmprb %0,1,%1,%2"
|
||||
+ [(set_attr "type" "logical")])
|
||||
+
|
||||
+;; Test byte membership within set of 8 bytes.
|
||||
+;;
|
||||
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
+;; represents a byte whose value is ignored in this context and
|
||||
+;; vv, the least significant byte, holds the byte value that is to
|
||||
+;; be tested for membership within the set specified by operand 2.
|
||||
+;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||
+;;
|
||||
+;; Return in target register operand 0 a value of 1 if vv equals one
|
||||
+;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
|
||||
+;; register operand 0 to 0. Note that the 8 byte values held within
|
||||
+;; operand 2 need not be unique.
|
||||
+;;
|
||||
+;; Though the instructions to which this expansion maps operate on
|
||||
+;; 64-bit registers, the current implementation requires that operands
|
||||
+;; 0 and 1 have mode SI as the high-order bits provide no information
|
||||
+;; that is not already available in the low-order bits. To avoid the
|
||||
+;; costs of data widening operations, future enhancements might allow
|
||||
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||
+(define_expand "cmpeqb"
|
||||
+ [(set (match_dup 3)
|
||||
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||
+ UNSPEC_CMPEQB))
|
||||
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
+ (if_then_else:SI (lt (match_dup 3)
|
||||
+ (const_int 0))
|
||||
+ (const_int -1)
|
||||
+ (if_then_else (gt (match_dup 3)
|
||||
+ (const_int 0))
|
||||
+ (const_int 1)
|
||||
+ (const_int 0))))]
|
||||
+ "TARGET_P9_MISC && TARGET_64BIT"
|
||||
+{
|
||||
+ operands[3] = gen_reg_rtx (CCmode);
|
||||
+})
|
||||
+
|
||||
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
+;; represents a byte whose value is ignored in this context and
|
||||
+;; vv, the least significant byte, holds the byte value that is to
|
||||
+;; be tested for membership within the set specified by operand 2.
|
||||
+;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||
+;;
|
||||
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
|
||||
+;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
|
||||
+;; set the GT bit to zero. The other 3 bits of the target CR register
|
||||
+;; are all set to 0.
|
||||
+(define_insn "*cmpeqb_internal"
|
||||
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||
+ UNSPEC_CMPEQB))]
|
||||
+ "TARGET_P9_MISC && TARGET_64BIT"
|
||||
+ "cmpeqb %0,%1,%2"
|
||||
+ [(set_attr "type" "logical")])
|
||||
|
||||
(define_insn "*nabs<mode>2_hw"
|
||||
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
Backport: https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=276211
|
||||
|
||||
This fixes potential failures with openmp and constants, such as
|
||||
|
||||
error: ‘*.LC0’ not specified in enclosing ‘parallel’
|
||||
|
||||
--- gcc/gimplify.c
|
||||
+++ gcc/gimplify.c
|
||||
@@ -7132,6 +7132,8 @@
|
||||
kind = lang_hooks.decls.omp_predetermined_sharing (decl);
|
||||
if (kind != OMP_CLAUSE_DEFAULT_UNSPECIFIED)
|
||||
default_kind = kind;
|
||||
+ else if (VAR_P (decl) && TREE_STATIC (decl) && DECL_IN_CONSTANT_POOL (decl))
|
||||
+ default_kind = OMP_CLAUSE_DEFAULT_SHARED;
|
||||
|
||||
switch (default_kind)
|
||||
{
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
# Template file for 'gcc'
|
||||
_majorver=9
|
||||
_minorver=${_majorver}.2
|
||||
_gmp_version=6.1.2
|
||||
_minorver=${_majorver}.3
|
||||
_gmp_version=6.2.0
|
||||
_mpfr_version=4.0.2
|
||||
_mpc_version=1.1.0
|
||||
_isl_version=0.21
|
||||
|
||||
pkgname=gcc
|
||||
version=${_minorver}.0
|
||||
revision=3
|
||||
revision=1
|
||||
short_desc="GNU Compiler Collection"
|
||||
maintainer="Enno Boland <gottox@voidlinux.org>"
|
||||
homepage="http://gcc.gnu.org"
|
||||
|
|
@ -20,8 +20,8 @@ distfiles="
|
|||
https://www.mpfr.org/mpfr-${_mpfr_version}/mpfr-${_mpfr_version}.tar.xz
|
||||
${GNU_SITE}/mpc/mpc-${_mpc_version}.tar.gz
|
||||
http://isl.gforge.inria.fr/isl-${_isl_version}.tar.bz2"
|
||||
checksum="ea6ef08f121239da5695f76c9b33637a118dcf63e24164422231917fa61fb206
|
||||
87b565e89a9a684fe4ebeeddb8399dce2599f9c9049854ca8c0dfbdea0e21912
|
||||
checksum="71e197867611f6054aa1119b13a0c0abac12834765fe2d81f35ac57f84f742d1
|
||||
258e6cd51b3fbdfc185c716d55f82c08aff57df0c6fbd143cf6ed561267a1526
|
||||
1d3be708604eae0e42d578ba93b390c2a145f17743a744d8f3f8c2ad5855a38a
|
||||
6985c538143c1208dcb1ac42cedad6ff52e267b47e5f970183a3e75125b43c2e
|
||||
d18ca11f8ad1a39ab6d03d3dcb3365ab416720fcb65b42d69f34f51bf0a0e859"
|
||||
|
|
|
|||
Loading…
Reference in a new issue