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gcc: update to 9.2.0 and enable gcc-go on musl

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q66 2019-09-07 19:13:12 +02:00 committed by Michael Aldridge
parent 067201d532
commit 2160419d90
6 changed files with 733 additions and 132 deletions
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200
srcpkgs/gcc/files/gccgo-musl.patch Normal file
View file

@ -0,0 +1,200 @@
This is not among the normal patches as these changes are musl specific and
there is no way to easily conditionalize it in source for some of the changes.
Souurce: Adélie Linux, q66
URL: https://code.foxkit.us/adelie/packages/tree/master/system/gcc
--- Makefile.in
+++ Makefile.in
@@ -46325,7 +46325,7 @@ configure-target-libgo:
esac; \
module_srcdir=libgo; \
rm -f no-such-file || : ; \
- CONFIG_SITE=no-such-file $(SHELL) \
+ CONFIG_SITE=no-such-file LIBS="-lucontext $$LIBS" $(SHELL) \
$$s/$$module_srcdir/configure \
--srcdir=$${topdir}/$$module_srcdir \
$(TARGET_CONFIGARGS) --build=${build_alias} --host=${target_alias} \
--- libgo/mksysinfo.sh
+++ libgo/mksysinfo.sh
@@ -379,11 +379,7 @@ fi
# Some basic types.
echo 'type Size_t _size_t' >> ${OUT}
echo "type Ssize_t _ssize_t" >> ${OUT}
-if grep '^const _HAVE_OFF64_T = ' gen-sysinfo.go > /dev/null 2>&1; then
- echo "type Offset_t _off64_t" >> ${OUT}
-else
- echo "type Offset_t _off_t" >> ${OUT}
-fi
+echo "type Offset_t _off_t" >> ${OUT}
echo "type Mode_t _mode_t" >> ${OUT}
echo "type Pid_t _pid_t" >> ${OUT}
echo "type Uid_t _uid_t" >> ${OUT}
--- libgo/go/runtime/mem_gccgo.go
+++ libgo/go/runtime/mem_gccgo.go
@@ -16,7 +16,7 @@ import (
//go:linkname sysFree runtime.sysFree
//extern mmap
-func sysMmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off uintptr) unsafe.Pointer
+func sysMmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off int64) unsafe.Pointer
//extern munmap
func munmap(addr unsafe.Pointer, length uintptr) int32
@@ -38,7 +38,7 @@ func init() {
}
}
-func mmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off uintptr) (unsafe.Pointer, int) {
+func mmap(addr unsafe.Pointer, n uintptr, prot, flags, fd int32, off int64) (unsafe.Pointer, int) {
p := sysMmap(addr, n, prot, flags, fd, off)
if uintptr(p) == _MAP_FAILED {
return nil, errno()
--- libgo/go/runtime/signal_gccgo.go
+++ libgo/go/runtime/signal_gccgo.go
@@ -111,7 +111,7 @@ func getsig(i uint32) uintptr {
if sigaction(i, nil, &sa) < 0 {
// On GNU/Linux glibc rejects attempts to call
// sigaction with signal 32 (SIGCANCEL) or 33 (SIGSETXID).
- if GOOS == "linux" && (i == 32 || i == 33) {
+ if GOOS == "linux" && (i == 32 || i == 33 || i == 34) {
return _SIG_DFL
}
throw("sigaction read failure")
--- libgo/go/syscall/errstr.go
+++ libgo/go/syscall/errstr.go
@@ -5,7 +5,6 @@
// license that can be found in the LICENSE file.
// +build !hurd
-// +build !linux
package syscall
--- libgo/go/syscall/errstr_glibc.go
+++ /dev/null
@@ -1,33 +0,0 @@
-// errstr_glibc.go -- GNU/Linux and GNU/Hurd specific error strings.
-
-// Copyright 2010 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-// We use this rather than errstr.go because on GNU/Linux sterror_r
-// returns a pointer to the error message, and may not use buf at all.
-
-// +build hurd linux
-
-package syscall
-
-import "unsafe"
-
-//sysnb strerror_r(errnum int, b []byte) (errstr *byte)
-//strerror_r(errnum _C_int, b *byte, len Size_t) *byte
-
-func Errstr(errnum int) string {
- a := make([]byte, 128)
- p := strerror_r(errnum, a)
- b := (*[1000]byte)(unsafe.Pointer(p))
- i := 0
- for b[i] != 0 {
- i++
- }
- // Lowercase first letter: Bad -> bad, but STREAM -> STREAM.
- if i > 1 && 'A' <= b[0] && b[0] <= 'Z' && 'a' <= b[1] && b[1] <= 'z' {
- c := b[0] + 'a' - 'A'
- return string(c) + string(b[1:i])
- }
- return string(b[:i])
-}
--- libgo/go/syscall/libcall_linux.go
+++ libgo/go/syscall/libcall_linux.go
@@ -206,19 +206,19 @@ func Gettid() (tid int) {
//sys Setxattr(path string, attr string, data []byte, flags int) (err error)
//setxattr(path *byte, name *byte, value *byte, size Size_t, flags _C_int) _C_int
-//sys splice(rfd int, roff *_loff_t, wfd int, woff *_loff_t, len int, flags int) (n int64, err error)
-//splice(rfd _C_int, roff *_loff_t, wfd _C_int, woff *_loff_t, len Size_t, flags _C_uint) Ssize_t
+//sys splice(rfd int, roff *_off_t, wfd int, woff *_off_t, len int, flags int) (n int64, err error)
+//splice(rfd _C_int, roff *_off_t, wfd _C_int, woff *_off_t, len Size_t, flags _C_uint) Ssize_t
func Splice(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error) {
- var lroff _loff_t
- var plroff *_loff_t
+ var lroff _off_t
+ var plroff *_off_t
if roff != nil {
- lroff = _loff_t(*roff)
+ lroff = _off_t(*roff)
plroff = &lroff
}
- var lwoff _loff_t
- var plwoff *_loff_t
+ var lwoff _off_t
+ var plwoff *_off_t
if woff != nil {
- lwoff = _loff_t(*woff)
+ lwoff = _off_t(*woff)
plwoff = &lwoff
}
n, err = splice(rfd, plroff, wfd, plwoff, len, flags)
--- libgo/mksigtab.sh
+++ libgo/mksigtab.sh
@@ -82,7 +82,7 @@ checksig _SIGPWR '{_SigNotify, "SIGPWR: power failure restart"}'
checksig _SIGEMT '{_SigThrow, "SIGEMT: emulate instruction executed"}'
checksig _SIGINFO '{_SigNotify, "SIGINFO: status request from keyboard"}'
checksig _SIGTHR '{_SigNotify, "SIGTHR: reserved"}'
-checksig _SIGPOLL '{_SigNotify, "SIGPOLL: pollable event occurred"}'
+#checksig _SIGPOLL '{_SigNotify, "SIGPOLL: pollable event occurred"}'
checksig _SIGWAITING '{_SigNotify, "SIGWAITING: reserved signal no longer used by"}'
checksig _SIGLWP '{_SigNotify, "SIGLWP: reserved signal no longer used by"}'
checksig _SIGFREEZE '{_SigNotify, "SIGFREEZE: special signal used by CPR"}'
@@ -95,10 +95,12 @@ checksig _SIGLOST ' {_SigNotify, "SIGLOST: resource lost (Sun); server died (G
# Special handling of signals 32 and 33 on GNU/Linux systems,
# because they are special to glibc.
+# Signal 34 is additionally special to Linux systems with musl.
if test "${GOOS}" = "linux"; then
- SIGLIST=$SIGLIST"_32__33_"
+ SIGLIST=$SIGLIST"_32__33__34_"
echo ' 32: {_SigSetStack + _SigUnblock, "signal 32"}, /* SIGCANCEL; see issue 6997 */'
echo ' 33: {_SigSetStack + _SigUnblock, "signal 33"}, /* SIGSETXID; see issues 3871, 9400, 12498 */'
+ echo ' 34: {_SigSetStack + _SigUnblock, "signal 34"}, /* see issue 30062 */'
fi
if test "${GOOS}" = "aix"; then
--- libgo/runtime/go-signal.c
+++ libgo/runtime/go-signal.c
@@ -222,7 +222,11 @@ getSiginfo(siginfo_t *info, void *context __attribute__((unused)))
#endif
#ifdef __PPC__
#ifdef __linux__
- ret.sigpc = ((ucontext_t*)(context))->uc_mcontext.regs->nip;
+ #ifdef __PPC64__
+ ret.sigpc = ((ucontext_t*)(context))->uc_mcontext.gp_regs[32];
+ #else
+ ret.sigpc = ((ucontext_t*)(context))->uc_mcontext.gregs[32];
+ #endif
#endif
#ifdef _AIX
ret.sigpc = ((ucontext_t*)(context))->uc_mcontext.jmp_context.iar;
@@ -343,7 +343,7 @@ dumpregs(siginfo_t *info __attribute__((unused)), void *context __attribute__((u
#endif
#endif
-#if defined(__PPC__) && defined(__LITTLE_ENDIAN__)
+#if defined(__PPC__) && defined(__LITTLE_ENDIAN__) && defined(__GLIBC__)
#ifdef __linux__
{
mcontext_t *m = &((ucontext_t*)(context))->uc_mcontext;
--- libgo/sysinfo.c
+++ libgo/sysinfo.c
@@ -73,9 +73,6 @@
#include <sys/times.h>
#include <sys/wait.h>
#include <sys/un.h>
-#if defined(HAVE_SYS_USER_H)
-#include <sys/user.h>
-#endif
#if defined(HAVE_SYS_UTSNAME_H)
#include <sys/utsname.h>
#endif

23
srcpkgs/gcc/patches/bug90756.patch
View file

@ -1,23 +0,0 @@
Bug 90756 - [7/8/9 Regression] g++ ICE in convert_move, at expr.c:218 on i686 and s390x
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90756
--- gcc/explow.c 2019/07/04 02:39:58 273035
+++ gcc/explow.c 2019/07/04 04:49:22 273036
@@ -892,16 +892,7 @@
tree type = TREE_TYPE (name);
int unsignedp = TYPE_UNSIGNED (type);
- machine_mode mode = TYPE_MODE (type);
-
- /* Bypass TYPE_MODE when it maps vector modes to BLKmode. */
- if (mode == BLKmode)
- {
- gcc_assert (VECTOR_TYPE_P (type));
- mode = type->type_common.mode;
- }
-
- machine_mode pmode = promote_mode (type, mode, &unsignedp);
+ machine_mode pmode = promote_mode (type, TYPE_MODE (type), &unsignedp);
if (punsignedp)
*punsignedp = unsignedp;

504
srcpkgs/gcc/patches/darn.patch Normal file
View file

@ -0,0 +1,504 @@
Upstream: yes
Reference: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91481
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=275170
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=275181
Fixes a security issue with the hardware random number generator
when compiling for POWER9. Since Void compiles for POWER8 by
default, it's not affected, but people building custom binaries
might be.
--- gcc/config/rs6000/altivec.md
+++ gcc/config/rs6000/altivec.md
@@ -80,9 +80,6 @@
UNSPEC_VUPKHPX
UNSPEC_VUPKLPX
UNSPEC_CONVERT_4F32_8I16
- UNSPEC_DARN
- UNSPEC_DARN_32
- UNSPEC_DARN_RAW
UNSPEC_DST
UNSPEC_DSTT
UNSPEC_DSTST
@@ -161,9 +158,6 @@
UNSPEC_BCDADD
UNSPEC_BCDSUB
UNSPEC_BCD_OVERFLOW
- UNSPEC_CMPRB
- UNSPEC_CMPRB2
- UNSPEC_CMPEQB
UNSPEC_VRLMI
UNSPEC_VRLNM
])
@@ -4101,223 +4095,6 @@
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "type" "vecsimple")])
-(define_insn "darn_32"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
- "TARGET_P9_MISC"
- "darn %0,0"
- [(set_attr "type" "integer")])
-
-(define_insn "darn_raw"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "darn %0,2"
- [(set_attr "type" "integer")])
-
-(define_insn "darn"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(const_int 0)] UNSPEC_DARN))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "darn %0,1"
- [(set_attr "type" "integer")])
-
-;; Test byte within range.
-;;
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
-;; represents a byte whose value is ignored in this context and
-;; vv, the least significant byte, holds the byte value that is to
-;; be tested for membership within the range specified by operand 2.
-;; The bytes of operand 2 are organized as xx:xx:hi:lo.
-;;
-;; Return in target register operand 0 a value of 1 if lo <= vv and
-;; vv <= hi. Otherwise, set register operand 0 to 0.
-;;
-;; Though the instructions to which this expansion maps operate on
-;; 64-bit registers, the current implementation only operates on
-;; SI-mode operands as the high-order bits provide no information
-;; that is not already available in the low-order bits. To avoid the
-;; costs of data widening operations, future enhancements might allow
-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
-(define_expand "cmprb"
- [(set (match_dup 3)
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")]
- UNSPEC_CMPRB))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (lt (match_dup 3)
- (const_int 0))
- (const_int -1)
- (if_then_else (gt (match_dup 3)
- (const_int 0))
- (const_int 1)
- (const_int 0))))]
- "TARGET_P9_MISC"
-{
- operands[3] = gen_reg_rtx (CCmode);
-})
-
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
-;; represents a byte whose value is ignored in this context and
-;; vv, the least significant byte, holds the byte value that is to
-;; be tested for membership within the range specified by operand 2.
-;; The bytes of operand 2 are organized as xx:xx:hi:lo.
-;;
-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
-;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
-;; 3 bits of the target CR register are all set to 0.
-(define_insn "*cmprb_internal"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")]
- UNSPEC_CMPRB))]
- "TARGET_P9_MISC"
- "cmprb %0,0,%1,%2"
- [(set_attr "type" "logical")])
-
-;; Set operand 0 register to -1 if the LT bit (0x8) of condition
-;; register operand 1 is on. Otherwise, set operand 0 register to 1
-;; if the GT bit (0x4) of condition register operand 1 is on.
-;; Otherwise, set operand 0 to 0. Note that the result stored into
-;; register operand 0 is non-zero iff either the LT or GT bits are on
-;; within condition register operand 1.
-(define_insn "setb_signed"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
- (const_int 0))
- (const_int -1)
- (if_then_else (gt (match_dup 1)
- (const_int 0))
- (const_int 1)
- (const_int 0))))]
- "TARGET_P9_MISC"
- "setb %0,%1"
- [(set_attr "type" "logical")])
-
-(define_insn "setb_unsigned"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
- (const_int 0))
- (const_int -1)
- (if_then_else (gtu (match_dup 1)
- (const_int 0))
- (const_int 1)
- (const_int 0))))]
- "TARGET_P9_MISC"
- "setb %0,%1"
- [(set_attr "type" "logical")])
-
-;; Test byte within two ranges.
-;;
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
-;; represents a byte whose value is ignored in this context and
-;; vv, the least significant byte, holds the byte value that is to
-;; be tested for membership within the range specified by operand 2.
-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
-;;
-;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
-;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
-;; operand 0 to 0.
-;;
-;; Though the instructions to which this expansion maps operate on
-;; 64-bit registers, the current implementation only operates on
-;; SI-mode operands as the high-order bits provide no information
-;; that is not already available in the low-order bits. To avoid the
-;; costs of data widening operations, future enhancements might allow
-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
-(define_expand "cmprb2"
- [(set (match_dup 3)
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")]
- UNSPEC_CMPRB2))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (lt (match_dup 3)
- (const_int 0))
- (const_int -1)
- (if_then_else (gt (match_dup 3)
- (const_int 0))
- (const_int 1)
- (const_int 0))))]
- "TARGET_P9_MISC"
-{
- operands[3] = gen_reg_rtx (CCmode);
-})
-
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
-;; represents a byte whose value is ignored in this context and
-;; vv, the least significant byte, holds the byte value that is to
-;; be tested for membership within the ranges specified by operand 2.
-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
-;;
-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
-;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
-;; Otherwise, set the GT bit to 0. The other 3 bits of the target
-;; CR register are all set to 0.
-(define_insn "*cmprb2_internal"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "gpc_reg_operand" "r")]
- UNSPEC_CMPRB2))]
- "TARGET_P9_MISC"
- "cmprb %0,1,%1,%2"
- [(set_attr "type" "logical")])
-
-;; Test byte membership within set of 8 bytes.
-;;
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
-;; represents a byte whose value is ignored in this context and
-;; vv, the least significant byte, holds the byte value that is to
-;; be tested for membership within the set specified by operand 2.
-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
-;;
-;; Return in target register operand 0 a value of 1 if vv equals one
-;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
-;; register operand 0 to 0. Note that the 8 byte values held within
-;; operand 2 need not be unique.
-;;
-;; Though the instructions to which this expansion maps operate on
-;; 64-bit registers, the current implementation requires that operands
-;; 0 and 1 have mode SI as the high-order bits provide no information
-;; that is not already available in the low-order bits. To avoid the
-;; costs of data widening operations, future enhancements might allow
-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
-(define_expand "cmpeqb"
- [(set (match_dup 3)
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_CMPEQB))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (if_then_else:SI (lt (match_dup 3)
- (const_int 0))
- (const_int -1)
- (if_then_else (gt (match_dup 3)
- (const_int 0))
- (const_int 1)
- (const_int 0))))]
- "TARGET_P9_MISC && TARGET_64BIT"
-{
- operands[3] = gen_reg_rtx (CCmode);
-})
-
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
-;; represents a byte whose value is ignored in this context and
-;; vv, the least significant byte, holds the byte value that is to
-;; be tested for membership within the set specified by operand 2.
-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
-;;
-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
-;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
-;; set the GT bit to zero. The other 3 bits of the target CR register
-;; are all set to 0.
-(define_insn "*cmpeqb_internal"
- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_CMPEQB))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "cmpeqb %0,%1,%2"
- [(set_attr "type" "logical")])
-
(define_expand "bcd<bcd_add_sub>_<code>"
[(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
--- gcc/config/rs6000/rs6000.md
+++ gcc/config/rs6000/rs6000.md
@@ -137,6 +137,9 @@
UNSPEC_LSQ
UNSPEC_FUSION_GPR
UNSPEC_STACK_CHECK
+ UNSPEC_CMPRB
+ UNSPEC_CMPRB2
+ UNSPEC_CMPEQB
UNSPEC_ADD_ROUND_TO_ODD
UNSPEC_SUB_ROUND_TO_ODD
UNSPEC_MUL_ROUND_TO_ODD
@@ -164,6 +167,9 @@
UNSPECV_EH_RR ; eh_reg_restore
UNSPECV_ISYNC ; isync instruction
UNSPECV_MFTB ; move from time base
+ UNSPECV_DARN ; darn 1 (deliver a random number)
+ UNSPECV_DARN_32 ; darn 2
+ UNSPECV_DARN_RAW ; darn 0
UNSPECV_NLGR ; non-local goto receiver
UNSPECV_MFFS ; Move from FPSCR
UNSPECV_MFFSL ; Move from FPSCR light instruction version
@@ -13853,6 +13859,224 @@
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
+;; Miscellaneous ISA 3.0 (power9) instructions
+
+(define_insn "darn_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
+ "TARGET_P9_MISC"
+ "darn %0,0"
+ [(set_attr "type" "integer")])
+
+(define_insn "darn_raw"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
+ "TARGET_P9_MISC && TARGET_64BIT"
+ "darn %0,2"
+ [(set_attr "type" "integer")])
+
+(define_insn "darn"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
+ "TARGET_P9_MISC && TARGET_64BIT"
+ "darn %0,1"
+ [(set_attr "type" "integer")])
+
+;; Test byte within range.
+;;
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
+;; represents a byte whose value is ignored in this context and
+;; vv, the least significant byte, holds the byte value that is to
+;; be tested for membership within the range specified by operand 2.
+;; The bytes of operand 2 are organized as xx:xx:hi:lo.
+;;
+;; Return in target register operand 0 a value of 1 if lo <= vv and
+;; vv <= hi. Otherwise, set register operand 0 to 0.
+;;
+;; Though the instructions to which this expansion maps operate on
+;; 64-bit registers, the current implementation only operates on
+;; SI-mode operands as the high-order bits provide no information
+;; that is not already available in the low-order bits. To avoid the
+;; costs of data widening operations, future enhancements might allow
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
+(define_expand "cmprb"
+ [(set (match_dup 3)
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
+ UNSPEC_CMPRB))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (if_then_else:SI (lt (match_dup 3)
+ (const_int 0))
+ (const_int -1)
+ (if_then_else (gt (match_dup 3)
+ (const_int 0))
+ (const_int 1)
+ (const_int 0))))]
+ "TARGET_P9_MISC"
+{
+ operands[3] = gen_reg_rtx (CCmode);
+})
+
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
+;; represents a byte whose value is ignored in this context and
+;; vv, the least significant byte, holds the byte value that is to
+;; be tested for membership within the range specified by operand 2.
+;; The bytes of operand 2 are organized as xx:xx:hi:lo.
+;;
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
+;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
+;; 3 bits of the target CR register are all set to 0.
+(define_insn "*cmprb_internal"
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
+ UNSPEC_CMPRB))]
+ "TARGET_P9_MISC"
+ "cmprb %0,0,%1,%2"
+ [(set_attr "type" "logical")])
+
+;; Set operand 0 register to -1 if the LT bit (0x8) of condition
+;; register operand 1 is on. Otherwise, set operand 0 register to 1
+;; if the GT bit (0x4) of condition register operand 1 is on.
+;; Otherwise, set operand 0 to 0. Note that the result stored into
+;; register operand 0 is non-zero iff either the LT or GT bits are on
+;; within condition register operand 1.
+(define_insn "setb_signed"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
+ (const_int 0))
+ (const_int -1)
+ (if_then_else (gt (match_dup 1)
+ (const_int 0))
+ (const_int 1)
+ (const_int 0))))]
+ "TARGET_P9_MISC"
+ "setb %0,%1"
+ [(set_attr "type" "logical")])
+
+(define_insn "setb_unsigned"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
+ (const_int 0))
+ (const_int -1)
+ (if_then_else (gtu (match_dup 1)
+ (const_int 0))
+ (const_int 1)
+ (const_int 0))))]
+ "TARGET_P9_MISC"
+ "setb %0,%1"
+ [(set_attr "type" "logical")])
+
+;; Test byte within two ranges.
+;;
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
+;; represents a byte whose value is ignored in this context and
+;; vv, the least significant byte, holds the byte value that is to
+;; be tested for membership within the range specified by operand 2.
+;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
+;;
+;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
+;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
+;; operand 0 to 0.
+;;
+;; Though the instructions to which this expansion maps operate on
+;; 64-bit registers, the current implementation only operates on
+;; SI-mode operands as the high-order bits provide no information
+;; that is not already available in the low-order bits. To avoid the
+;; costs of data widening operations, future enhancements might allow
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
+(define_expand "cmprb2"
+ [(set (match_dup 3)
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
+ UNSPEC_CMPRB2))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (if_then_else:SI (lt (match_dup 3)
+ (const_int 0))
+ (const_int -1)
+ (if_then_else (gt (match_dup 3)
+ (const_int 0))
+ (const_int 1)
+ (const_int 0))))]
+ "TARGET_P9_MISC"
+{
+ operands[3] = gen_reg_rtx (CCmode);
+})
+
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
+;; represents a byte whose value is ignored in this context and
+;; vv, the least significant byte, holds the byte value that is to
+;; be tested for membership within the ranges specified by operand 2.
+;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
+;;
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
+;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
+;; Otherwise, set the GT bit to 0. The other 3 bits of the target
+;; CR register are all set to 0.
+(define_insn "*cmprb2_internal"
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
+ UNSPEC_CMPRB2))]
+ "TARGET_P9_MISC"
+ "cmprb %0,1,%1,%2"
+ [(set_attr "type" "logical")])
+
+;; Test byte membership within set of 8 bytes.
+;;
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
+;; represents a byte whose value is ignored in this context and
+;; vv, the least significant byte, holds the byte value that is to
+;; be tested for membership within the set specified by operand 2.
+;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
+;;
+;; Return in target register operand 0 a value of 1 if vv equals one
+;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
+;; register operand 0 to 0. Note that the 8 byte values held within
+;; operand 2 need not be unique.
+;;
+;; Though the instructions to which this expansion maps operate on
+;; 64-bit registers, the current implementation requires that operands
+;; 0 and 1 have mode SI as the high-order bits provide no information
+;; that is not already available in the low-order bits. To avoid the
+;; costs of data widening operations, future enhancements might allow
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
+(define_expand "cmpeqb"
+ [(set (match_dup 3)
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_CMPEQB))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (if_then_else:SI (lt (match_dup 3)
+ (const_int 0))
+ (const_int -1)
+ (if_then_else (gt (match_dup 3)
+ (const_int 0))
+ (const_int 1)
+ (const_int 0))))]
+ "TARGET_P9_MISC && TARGET_64BIT"
+{
+ operands[3] = gen_reg_rtx (CCmode);
+})
+
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
+;; represents a byte whose value is ignored in this context and
+;; vv, the least significant byte, holds the byte value that is to
+;; be tested for membership within the set specified by operand 2.
+;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
+;;
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
+;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
+;; set the GT bit to zero. The other 3 bits of the target CR register
+;; are all set to 0.
+(define_insn "*cmpeqb_internal"
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_CMPEQB))]
+ "TARGET_P9_MISC && TARGET_64BIT"
+ "cmpeqb %0,%1,%2"
+ [(set_attr "type" "logical")])
(define_insn "*nabs<mode>2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")

11
srcpkgs/gcc/patches/libffi_gnulinux.patch Normal file
View file

@ -0,0 +1,11 @@
--- libffi/src/closures.c.orig
+++ libffi/src/closures.c
@@ -34,7 +34,7 @@
#include <ffi_common.h>
#if !FFI_MMAP_EXEC_WRIT && !FFI_EXEC_TRAMPOLINE_TABLE
-# if __gnu_linux__ && !defined(__ANDROID__)
+# if __linux__ && !defined(__ANDROID__)
/* This macro indicates it may be forbidden to map anonymous memory
with both write and execute permission. Code compiled when this
option is defined will attempt to map such pages once, but if it

88
srcpkgs/gcc/patches/non-nullness.patch
View file

@ -1,88 +0,0 @@
Source: 2019-06-21 Jeff Law <law@redhat.com>
Upstream: yes
Reason: PR tree-optimization/90949
* tree-ssa-copy.c (fini_copy_prop): Use reset_flow_sensitive_info.
* tree-ssanames.c (reset_flow_sensitive_info): Reset non-null state.
--- gcc/tree-ssa-copy.c 2019-01-01 13:31:55.000000000 +0100
+++ gcc/tree-ssa-copy.c 2019-06-26 18:50:01.030395471 +0200
@@ -545,13 +545,12 @@
duplicate_ssa_name_ptr_info (copy_of[i].value,
SSA_NAME_PTR_INFO (var));
/* Points-to information is cfg insensitive,
- but alignment info might be cfg sensitive, if it
- e.g. is derived from VRP derived non-zero bits.
- So, do not copy alignment info if the two SSA_NAMEs
- aren't defined in the same basic block. */
+ but [E]VRP might record context sensitive alignment
+ info, non-nullness, etc. So reset context sensitive
+ info if the two SSA_NAMEs aren't defined in the same
+ basic block. */
if (var_bb != copy_of_bb)
- mark_ptr_info_alignment_unknown
- (SSA_NAME_PTR_INFO (copy_of[i].value));
+ reset_flow_sensitive_info (copy_of[i].value);
}
else if (!POINTER_TYPE_P (TREE_TYPE (var))
&& SSA_NAME_RANGE_INFO (var)
--- gcc/tree-ssanames.c 2019-03-18 14:59:11.000000000 +0100
+++ gcc/tree-ssanames.c 2019-06-26 18:50:11.282394906 +0200
@@ -820,7 +820,12 @@
{
/* points-to info is not flow-sensitive. */
if (SSA_NAME_PTR_INFO (name))
- mark_ptr_info_alignment_unknown (SSA_NAME_PTR_INFO (name));
+ {
+ /* [E]VRP can derive context sensitive alignment info and
+ non-nullness properties. We must reset both. */
+ mark_ptr_info_alignment_unknown (SSA_NAME_PTR_INFO (name));
+ SSA_NAME_PTR_INFO (name)->pt.null = 1;
+ }
}
else
SSA_NAME_RANGE_INFO (name) = NULL;
--- /dev/null
+++ gcc/testsuite/gcc.c-torture/pr90949.c 2019-06-26 18:53:16.870384679 +0200
@@ -0,0 +1,42 @@
+void __attribute__ ((noipa, noinline)) my_puts (const char *str) { }
+
+void __attribute__ ((noipa, noinline)) my_free (void *p) { }
+
+
+struct Node
+{
+ struct Node *child;
+};
+
+struct Node space[2] = { };
+
+struct Node * __attribute__ ((noipa, noinline)) my_malloc (int bytes)
+{
+ return &space[0];
+}
+
+void
+walk (struct Node *module, int cleanup)
+{
+ if (module == 0)
+ {
+ return;
+ }
+ if (!cleanup)
+ {
+ my_puts ("No cleanup");
+ }
+ walk (module->child, cleanup);
+ if (cleanup)
+ {
+ my_free (module);
+ }
+}
+
+int
+main ()
+{
+ struct Node *node = my_malloc (sizeof (struct Node));
+ node->child = 0;
+ walk (node, 1);
+}

39
srcpkgs/gcc/template
View file

@ -1,14 +1,14 @@
# Template file for 'gcc'
_majorver=9
_minorver=${_majorver}.1
_minorver=${_majorver}.2
_gmp_version=6.1.2
_mpfr_version=4.0.1
_mpfr_version=4.0.2
_mpc_version=1.1.0
_isl_version=0.19
_isl_version=0.21
pkgname=gcc
version=${_minorver}.0
revision=3
revision=1
short_desc="GNU Compiler Collection"
maintainer="Enno Boland <gottox@voidlinux.org>"
homepage="http://gcc.gnu.org"
@ -20,17 +20,18 @@ distfiles="
https://www.mpfr.org/mpfr-${_mpfr_version}/mpfr-${_mpfr_version}.tar.xz
${GNU_SITE}/mpc/mpc-${_mpc_version}.tar.gz
http://isl.gforge.inria.fr/isl-${_isl_version}.tar.bz2"
checksum="79a66834e96a6050d8fe78db2c3b32fb285b230b855d0a66288235bc04b327a0
checksum="ea6ef08f121239da5695f76c9b33637a118dcf63e24164422231917fa61fb206
87b565e89a9a684fe4ebeeddb8399dce2599f9c9049854ca8c0dfbdea0e21912
67874a60826303ee2fb6affc6dc0ddd3e749e9bfcb4c8655e3953d0458a6e16e
1d3be708604eae0e42d578ba93b390c2a145f17743a744d8f3f8c2ad5855a38a
6985c538143c1208dcb1ac42cedad6ff52e267b47e5f970183a3e75125b43c2e
d59726f34f7852a081fbd3defd1ab2136f174110fc2e0c8d10bb122173fa9ed8"
d18ca11f8ad1a39ab6d03d3dcb3365ab416720fcb65b42d69f34f51bf0a0e859"
nopie=yes
lib32disabled=yes
bootstrap=yes
replaces="gcc-gcj<7.2.0 gcc-gcj-jdk-compat<7.2.0 libmpx>=0 libmpx-devel>=0"
alternatives="cc:cc:/usr/bin/gcc"
nocross=yes
if [ "$CHROOT_READY" ]; then
hostmakedepends="perl flex"
@ -69,12 +70,11 @@ if [ "$CHROOT_READY" ]; then
subpackages+=" gcc-fortran libgfortran-devel libgfortran"
if [ -z "$CROSS_BUILD" ]; then
subpackages+=" gcc-objc gcc-objc++ libobjc-devel libobjc"
case "$XBPS_TARGET_MACHINE" in
*-musl) # Go won't link for musl libc
;;
*) subpackages+=" gcc-go gcc-go-tools libgo-devel libgo"
;;
esac
subpackages+=" gcc-go gcc-go-tools libgo-devel libgo"
# we need this for gcc-go on musl
if [ "$XBPS_TARGET_LIBC" = "musl" ]; then
makedepends+=" libucontext-devel"
fi
fi
fi
@ -162,7 +162,10 @@ pre_configure() {
# _FORTIFY_SOURCE needs an optimization level.
sed -i "/ac_cpp=/s/\$CPPFLAGS/\$CPPFLAGS -O2/" {gcc,libiberty}/configure
case "$XBPS_TARGET_MACHINE" in
*-musl) patch -p1 -i ${FILESDIR}/libgnarl-musl.patch ;;
*-musl)
patch -p1 -i ${FILESDIR}/libgnarl-musl.patch
patch -p0 -i ${FILESDIR}/gccgo-musl.patch
;;
esac
}
do_configure() {
@ -225,13 +228,7 @@ do_configure() {
export LD_LIBRARY_PATH="${XBPS_MASTERDIR}/usr/lib"
_args+=" --build=${_triplet}"
else
_langs="c,c++,objc,obj-c++,fortran,lto"
case "$XBPS_TARGET_MACHINE" in
*-musl) # Linking libgo.so is broken for musl libc
;;
*) _langs+=",go"
;;
esac
_langs="c,c++,objc,obj-c++,go,fortran,lto"
_args+=" --build=${_triplet}"
_args+=" --enable-fast-character"
fi