From 3c3fb302e866090ac0587518fa857f5d74547b28 Mon Sep 17 00:00:00 2001 From: q66 Date: Mon, 28 Jan 2019 01:29:55 +0100 Subject: [PATCH] 0ad: patch for ppc64 [ci skip] --- srcpkgs/0ad/patches/ppc64-spidermonkey.patch | 43 ++++ srcpkgs/0ad/patches/ppc64.patch | 242 +++++++++++++++++++ 2 files changed, 285 insertions(+) create mode 100644 srcpkgs/0ad/patches/ppc64-spidermonkey.patch create mode 100644 srcpkgs/0ad/patches/ppc64.patch diff --git a/srcpkgs/0ad/patches/ppc64-spidermonkey.patch b/srcpkgs/0ad/patches/ppc64-spidermonkey.patch new file mode 100644 index 0000000000..948d1c6603 --- /dev/null +++ b/srcpkgs/0ad/patches/ppc64-spidermonkey.patch @@ -0,0 +1,43 @@ +--- libraries/source/spidermonkey/patch.sh ++++ libraries/source/spidermonkey/patch.sh +@@ -53,3 +53,4 @@ patch -p1 < ../FixTracelogger.diff + # Based on: https://svnweb.freebsd.org/ports/head/sysutils/py-psutil121/files/patch-_psutil_bsd.c?revision=436575&view=markup + # Related: https://bugzilla.mozilla.org/show_bug.cgi?id=1238983 + patch -p0 < ../FixpsutilFreeBSD.diff ++patch -p0 < ../ppc64.diff +--- /dev/null ++++ libraries/source/spidermonkey/ppc64.diff +@@ -0,0 +1,33 @@ ++--- js/src/jit/CodeGenerator.cpp +++++ js/src/jit/CodeGenerator.cpp ++@@ -3464,12 +3464,12 @@ CodeGenerator::visitCallDirectEvalV(LCallDirectEvalV* lir) ++ callVM(DirectEvalValueInfo, lir); ++ } ++ ++-// Registers safe for use before generatePrologue(). ++-static const uint32_t EntryTempMask = Registers::TempMask & ~(1 << OsrFrameReg.code()); ++- ++ void ++ CodeGenerator::generateArgumentsChecks(bool bailout) ++ { +++ // Registers safe for use before generatePrologue(). +++ static const uint32_t EntryTempMask = Registers::TempMask & ~(1 << OsrFrameReg.code()); +++ ++ // This function can be used the normal way to check the argument types, ++ // before entering the function and bailout when arguments don't match. ++ // For debug purpose, this is can also be used to force/check that the ++--- js/src/jit/none/MacroAssembler-none.h +++++ js/src/jit/none/MacroAssembler-none.h ++@@ -131,6 +131,12 @@ class Assembler : public AssemblerShared ++ static void ToggleCall(CodeLocationLabel, bool) { MOZ_CRASH(); } ++ ++ static uintptr_t GetPointer(uint8_t*) { MOZ_CRASH(); } +++ +++ void verifyHeapAccessDisassembly(uint32_t begin, uint32_t end, +++ const Disassembler::HeapAccess &heapAccess) +++ { +++ MOZ_CRASH(); +++ } ++ }; ++ ++ class Operand diff --git a/srcpkgs/0ad/patches/ppc64.patch b/srcpkgs/0ad/patches/ppc64.patch new file mode 100644 index 0000000000..e409c0ed91 --- /dev/null +++ b/srcpkgs/0ad/patches/ppc64.patch @@ -0,0 +1,242 @@ +--- build/premake/premake4.lua ++++ build/premake/premake4.lua +@@ -88,6 +88,8 @@ else + arch = "arm" + elseif string.find(machine, "aarch64") == 1 then + arch = "aarch64" ++ elseif string.find(machine, "ppc64") == 1 or string.find(machine, "powerpc64") == 1 then ++ arch = "ppc64" + else + print("WARNING: Cannot determine architecture from GCC, assuming x86") + end +@@ -823,6 +825,8 @@ function setup_all_libs () + table.insert(source_dirs, "lib/sysdep/arch/x86_x64"); + elseif arch == "arm" then + table.insert(source_dirs, "lib/sysdep/arch/arm"); ++ elseif arch == "ppc64" then ++ table.insert(source_dirs, "lib/sysdep/arch/ppc64"); + elseif arch == "aarch64" then + table.insert(source_dirs, "lib/sysdep/arch/aarch64"); + end +--- build/premake/premake5.lua ++++ build/premake/premake5.lua +@@ -81,6 +81,8 @@ else + arch = "arm" + elseif string.find(machine, "aarch64") == 1 then + arch = "aarch64" ++ elseif string.find(machine, "ppc64") == 1 or string.find(machine, "powerpc64") == 1 then ++ arch = "ppc64" + else + print("WARNING: Cannot determine architecture from GCC, assuming x86") + end +@@ -823,6 +825,8 @@ function setup_all_libs () + table.insert(source_dirs, "lib/sysdep/arch/x86_x64"); + elseif arch == "arm" then + table.insert(source_dirs, "lib/sysdep/arch/arm"); ++ elseif arch == "ppc64" then ++ table.insert(source_dirs, "lib/sysdep/arch/ppc64"); + elseif arch == "aarch64" then + table.insert(source_dirs, "lib/sysdep/arch/aarch64"); + end +--- libraries/source/nvtt/src/src/nvcore/poshlib/posh.h ++++ libraries/source/nvtt/src/src/nvcore/poshlib/posh.h +@@ -663,7 +663,7 @@ Metrowerks: + ** the MIPS series, so we have to be careful about those. + ** ---------------------------------------------------------------------------- + */ +-#if defined POSH_CPU_X86 || defined POSH_CPU_AXP || defined POSH_CPU_STRONGARM || defined POSH_CPU_AARCH64 || defined POSH_OS_WIN32 || defined POSH_OS_WINCE || defined __MIPSEL__ ++#if defined POSH_CPU_X86 || defined POSH_CPU_AXP || defined POSH_CPU_STRONGARM || defined POSH_CPU_AARCH64 || defined POSH_OS_WIN32 || defined POSH_OS_WINCE || defined __MIPSEL__ || __LITTLE_ENDIAN__ + # define POSH_ENDIAN_STRING "little" + # define POSH_LITTLE_ENDIAN 1 + #else +--- libraries/source/nvtt/src/src/nvmath/Plane.h ++++ libraries/source/nvtt/src/src/nvmath/Plane.h +@@ -6,6 +6,10 @@ + #include + #include + ++#if NV_USE_ALTIVEC ++#undef vector ++#endif ++ + namespace nv + { + class Matrix; +--- libraries/source/nvtt/src/src/nvtt/squish/simd_ve.h ++++ libraries/source/nvtt/src/src/nvtt/squish/simd_ve.h +@@ -1,6 +1,7 @@ + /* ----------------------------------------------------------------------------- + + Copyright (c) 2006 Simon Brown si@sjbrown.co.uk ++ Copyright (c) 2016 Raptor Engineering, LLC + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the +@@ -31,7 +32,7 @@ + + namespace squish { + +-#define VEC4_CONST( X ) Vec4( ( vector float )( X ) ) ++#define VEC4_CONST( X ) Vec4( vec_splats( (float)X ) ) + + class Vec4 + { +@@ -96,7 +97,7 @@ public: + + Vec4& operator*=( Arg v ) + { +- m_v = vec_madd( m_v, v.m_v, ( vector float )( -0.0f ) ); ++ m_v = vec_madd( m_v, v.m_v, vec_splats( -0.0f ) ); + return *this; + } + +@@ -112,7 +113,7 @@ public: + + friend Vec4 operator*( Vec4::Arg left, Vec4::Arg right ) + { +- return Vec4( vec_madd( left.m_v, right.m_v, ( vector float )( -0.0f ) ) ); ++ return Vec4( vec_madd( left.m_v, right.m_v, vec_splats( -0.0f ) ) ); + } + + //! Returns a*b + c +@@ -133,7 +134,7 @@ public: + vector float estimate = vec_re( v.m_v ); + + // one round of Newton-Rhaphson refinement +- vector float diff = vec_nmsub( estimate, v.m_v, ( vector float )( 1.0f ) ); ++ vector float diff = vec_nmsub( estimate, v.m_v, vec_splats( 1.0f ) ); + return Vec4( vec_madd( diff, estimate, estimate ) ); + } + +--- source/graphics/TextureConverter.cpp ++++ source/graphics/TextureConverter.cpp +@@ -45,6 +45,10 @@ struct BufferOutputHandler : public nvtt::OutputHandler + { + } + ++ virtual void endImage() ++ { ++ } ++ + virtual bool writeData(const void* data, int size) + { + size_t off = buffer.size(); +--- source/lib/alignment.h ++++ source/lib/alignment.h +@@ -80,7 +80,18 @@ static const size_t cacheLineSize = 64; // (L2) + // MMU pages + // + ++#ifdef __PPC64__ ++// NOTE: ppc64 can operate in either 4k or 64k page size mode ++// If the define page size is larger than the active page size, ++// the allocator functions normally. If the defined page size ++// is less than the active page size, the allocator fails tests. ++// ++// Define the page size to the maximum known architectural page ++// size on ppc64 systems. ++static const size_t g_PageSize = 64 * 1024; // 64 KB ++#else + static const size_t g_PageSize = 4 * 1024; // 4 KB ++#endif + static const size_t g_LargePageSize = 2 * 1024 * 1024; // 2 MB + + +--- source/lib/byte_order.h ++++ source/lib/byte_order.h +@@ -33,7 +33,7 @@ + #ifndef BYTE_ORDER + # define LITTLE_ENDIAN 0x4321 + # define BIG_ENDIAN 0x1234 +-# if ARCH_IA32 || ARCH_IA64 || ARCH_AMD64 || ARCH_ALPHA || ARCH_ARM || ARCH_AARCH64 || ARCH_MIPS || defined(__LITTLE_ENDIAN__) ++# if ARCH_IA32 || ARCH_IA64 || ARCH_AMD64 || ARCH_ALPHA || ARCH_ARM || ARCH_AARCH64 || ARCH_PPC64 || ARCH_MIPS || defined(__LITTLE_ENDIAN__) + # define BYTE_ORDER LITTLE_ENDIAN + # else + # define BYTE_ORDER BIG_ENDIAN +--- source/lib/sysdep/arch.h ++++ source/lib/sysdep/arch.h +@@ -64,6 +64,12 @@ + #else + # define ARCH_AARCH64 0 + #endif ++// .. PowerPC64 (PPC64) ++#if defined(__PPC64__) ++# define ARCH_PPC64 1 ++#else ++# define ARCH_PPC64 0 ++#endif + // .. MIPS + #if defined(__MIPS__) || defined(__mips__) || defined(__mips) + # define ARCH_MIPS 1 +@@ -72,7 +78,7 @@ + #endif + + // ensure exactly one architecture has been detected +-#if (ARCH_IA32+ARCH_IA64+ARCH_AMD64+ARCH_ALPHA+ARCH_ARM+ARCH_AARCH64+ARCH_MIPS) != 1 ++#if (ARCH_IA32+ARCH_IA64+ARCH_AMD64+ARCH_ALPHA+ARCH_ARM+ARCH_AARCH64+ARCH_PPC64+ARCH_MIPS) != 1 + # error "architecture not correctly detected (either none or multiple ARCH_* defined)" + #endif + +--- /dev/null ++++ source/lib/sysdep/arch/ppc64/ppc64.cpp +@@ -0,0 +1,50 @@ ++/* Copyright (C) 2012 Wildfire Games ++ * Copyright (C) 2018 Raptor Engineering, LLC ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining ++ * a copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sublicense, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* ++ * routines specific to POWER ++ */ ++ ++#include "precompiled.h" ++ ++#include "lib/sysdep/cpu.h" ++ ++intptr_t cpu_AtomicAdd(volatile intptr_t* location, intptr_t increment) ++{ ++ return __sync_fetch_and_add(location, increment); ++} ++ ++bool cpu_CAS(volatile intptr_t* location, intptr_t expected, intptr_t newValue) ++{ ++ return __sync_bool_compare_and_swap(location, expected, newValue); ++} ++ ++bool cpu_CAS64(volatile i64* location, i64 expected, i64 newValue) ++{ ++ return __sync_bool_compare_and_swap(location, expected, newValue); ++} ++ ++const char* cpu_IdentifierString() ++{ ++ return "IBM POWER"; // TODO ++} +--- source/ps/GameSetup/HWDetect.cpp ++++ source/ps/GameSetup/HWDetect.cpp +@@ -247,6 +247,7 @@ void RunHardwareDetection() + scriptInterface.SetProperty(settings, "arch_amd64", ARCH_AMD64); + scriptInterface.SetProperty(settings, "arch_arm", ARCH_ARM); + scriptInterface.SetProperty(settings, "arch_aarch64", ARCH_AARCH64); ++ scriptInterface.SetProperty(settings, "arch_ppc64", ARCH_PPC64); + + #ifdef NDEBUG + scriptInterface.SetProperty(settings, "build_debug", 0);